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4 Commits

Author SHA1 Message Date
Andreas Olofsson
d275406aa6 Reset timing optimization 
- holding rx in reset state until tx is done
- removing reset from all pipeline registers
- removing reset from oddr/iddr
- the idea is to keep things quiet not to block in lots of places. The only real block needed is in the FIFO to keep "noise" from propagating past the link. The link should be kept in a safe reset state until the rx fram is stable and the clock is running so that the pipe can be cleaned out.
 2015-10-08 10:34:59 -04:00
Andreas Olofsson
e1f17b2fa1 Fixing PLL feedback path 2015-10-07 21:58:30 -04:00
Andreas Olofsson
cd597cd5b1 Fixing RX reset (again!) 
-async assert
-sync deassert
 2015-10-07 20:37:49 -04:00
Andreas Olofsson
4477f55cf5 Separating clocks for tx/rx 
- more modular, understandable, reusable
 2015-10-07 19:08:32 -04:00