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434 Commits

Author SHA1 Message Date
Patrik Lindström
9d71189f93 Changing the receiver to use both frame signals 
Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>
 2015-08-24 21:39:31 +02:00
Patrik Lindström
f9c2a5abf3 moving idelay controller to eclocks.v 
Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>
 2015-08-24 21:08:49 +02:00
Andreas Olofsson
9bc40a8355 Fixing wait issue 
-Removing the wait signal from the pipeline
-Assumption is that the prog_full is used on fifo, allowing two entries
to be captured in fifo.
-May revisit this at some time...
 2015-08-14 17:13:52 -04:00
Andreas Olofsson
ede8656081 Fixing mutual exclusive bug on receiver 
-When a read response is detected, there should be no spurious transactions to the RD/WR request fifos.
-Move the "filter" backt to the erx_protocol block
-Removed the remap bypass signal (was hacky)
-Passes simulations again..
 2015-08-14 15:37:37 -04:00
Andreas Olofsson
21686d31cc Reorg for xilinx projects 
-making more modular
-still need to clean up duplucate files
 2015-08-08 12:29:00 -04:00
Andreas Olofsson
b0a321a588 Clarified enable/disable status 
-For now RX/TX is always on
-At some point make default off?
 2015-08-07 09:25:41 -04:00
Andreas Olofsson
8e32299f2c Copyright cleanup 2015-08-07 09:19:37 -04:00
Andreas Olofsson
617e5f76de Updating interface description 2015-08-07 09:15:10 -04:00
Andreas Olofsson
f908acc259 Updating docs 
-clarifications
-removing TX DMA
 2015-08-07 09:09:42 -04:00
Andreas Olofsson
7df92eb1f0 Removing DMA from transmit 
* Seems like a useless feature. Why autogenerate the transactions at the transmit side. This should always be done at the receive side to minimize bits moving across the link.  Can't really see a use for it anymore so I am removing it.
* If you want to hack the design to reduce latency, you can always grab the raw etx_core and drive signals directly through write port.
* May consider adding a fourth port to etx to allow bypassing  the link interfac?
* Add an ifdef to bypass the fifos?
 2015-08-07 09:05:11 -04:00
Andreas Olofsson
5e50d78c51 Merge branch 'master' of https://github.com/parallella/oh 2015-08-07 07:56:44 -04:00
Andreas Olofsson
36e8f78370 README changes and various fixes 2015-08-07 07:56:30 -04:00
Andreas Olofsson
cbc029521b Update README.md 2015-08-04 18:08:02 -04:00
Ola Jeppsson
4df38ca35e elink: Update scripts 
Use paths relative top top_srcdir (so scripts can be run from any
directory).
Add missing files
elink_example was renamed to axi_elink?

Fails at placement.

Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2015-07-05 23:51:19 +02:00
Ola Jeppsson
3db4e49675 elink: Convert package_axi_elink to use helper script 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2015-07-05 19:43:32 +02:00
Andreas Olofsson
9fb9dc1cd5 Adding IP packaging script 2015-07-02 16:58:43 -04:00
Andreas Olofsson
9379484f65 Fifo parameter change 
-Changing parameter name to DW
-Making depth 32 for axi interfaces
(tune this later...)
 2015-07-02 16:55:42 -04:00
Andreas Olofsson
f1b37ab4c4 Ephycard should not be default 2015-07-02 16:54:31 -04:00
Andreas Olofsson
d6f61784b0 Update dv paths 
-includes inside files (methodology change)
-adding ip paths
 2015-07-02 16:48:14 -04:00
Andreas Olofsson
e28cd3cb97 Adding search path for include file 2015-07-02 16:47:07 -04:00
Andreas Olofsson
368836ab9b Adding back a better fufu test vector 2015-07-02 16:46:33 -04:00
Patrik Lindström
a20c9f25ec clean up 2015-07-02 15:01:33 +02:00
Patrik Lindström
4a749bf2d8 timing fixes 2015-07-01 00:14:46 +02:00
Patrik Lindström
6d13611f21 script fixes 2015-06-30 16:02:39 +02:00
Patrik Lindström
667c7cb6a8 script fixes 2015-06-30 14:56:27 +02:00
Patrik Lindström
a284dff462 Bug fixes 2015-06-30 14:04:16 +02:00
Patrik Lindström
634ff371ac Bug fixes 2015-06-30 13:32:05 +02:00
Patrik Lindström
48fdf2d782 Added iostandard parameter 2015-06-30 12:44:22 +02:00
Patrik Lindström
f232d9d297 Changed rx_ref_clk PLL divider 2015-06-30 12:35:38 +02:00
Patrik Lindström
8c0dbffb61 Added different IDW for m_axi and s_axi 2015-06-30 12:31:14 +02:00
Andreas Olofsson
537bb6a330 Cleanup 2015-06-25 22:14:19 -04:00
Andreas Olofsson
e960b6f7c0 Adding IP package reference script 2015-06-25 22:14:05 -04:00
Andreas Olofsson
d9155f6538 Placeholder for elink 2015-06-25 16:17:20 -04:00
Andreas Olofsson
eb7028fdbf Reorg 2015-06-25 16:13:20 -04:00
Andreas Olofsson
badac2aa76 Name changes for signal grouping 2015-06-25 16:09:05 -04:00
Andreas Olofsson
2cbf91b07b Making reset sync in emmu 2015-05-23 22:26:15 -04:00
Andreas Olofsson
c9f64a2fb2 Fixing dv to check axi_elink 
-Need to split these, getting too cumbersome
 2015-05-21 22:56:23 -04:00
Andreas Olofsson
24d824f080 Fixing read response address 
-using `define from elink_regmap (ie 'D')
 2015-05-20 15:04:29 -04:00
Andreas Olofsson
7f0f858b92 Letting read response packets through 
-Needed for loopback testing
 2015-05-20 15:03:22 -04:00
Andreas Olofsson
a60de7fb30 Adding readback on axi_elink 
-Another cludgy memory
-Note that current esaxi doesn't support pushback so we have to hack the test to avoid read/write contention on this port.
 2015-05-19 23:53:05 -04:00
Andreas Olofsson
b1c3b3fb8c Adding filtering to ecfg_if 
-Avoids garbage writing coming back to esaxi
 2015-05-19 23:52:00 -04:00
Andreas Olofsson
005c9872dd Removing timeout from logic 
-Should be direct interface to esaxi
 2015-05-19 23:51:17 -04:00
Andreas Olofsson
7d524d0f68 Changing axi interface <--> elink protocol 
-Now consistant with packet, access, wait protocol
 2015-05-19 22:08:41 -04:00
Andreas Olofsson
8d3cbf8257 Clean axi_elink module 
-Clocks included inside for easy integration
-Another version might have the clocks and reset as inputs instead
 2015-05-19 22:07:16 -04:00
Andreas Olofsson
6d9731f14a Including environment for axi_elink 
-Should probably split this into separate environments
-Getting bulky and ugly...
 2015-05-19 22:06:15 -04:00
Andreas Olofsson
451a1fa925 MILESTONE: Bursts working!!! 
-Fairly clean minimalist design
-Complete redesign
-Need to do random read/write testing to make sure
-Speed?
 2015-05-18 15:38:30 -04:00
Andreas Olofsson
665876cfb4 Adding bursting to test bench 2015-05-18 15:37:46 -04:00
Andreas Olofsson
41f97e45ff Converting to synchronous reset 2015-05-17 23:00:53 -04:00
Andreas Olofsson
ae8d4b4dcd Adding more reports 
-check_timing is a crucial summary
 2015-05-17 22:35:15 -04:00
Andreas Olofsson
559ffcc6e0 File name changes and additions 2015-05-17 22:34:42 -04:00