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16 Commits

Author SHA1 Message Date
Andreas.Olofsson
d6f5de24d7 Changing hierarchy to promote blocks 2020-01-28 18:12:57 -05:00
Andreas Olofsson
7094173ae9 Reorg! Why?
- The top level directory was not scaling, too imposing
- Friendlier to download a repo and see a finite number of top level dirs
- We are just getting started...
2016-03-22 08:13:40 -04:00
Andreas Olofsson
14614bcfa5 Adding new clock signals to axi testbench 2016-03-08 19:35:25 -05:00
Andreas Olofsson
e8794b780c Simplifying axi_elink testbench
- Too much junk in there, couldn't understand my own logic 4 weeks later...
- emesh_if is a disaster, I have yet to find a way to write code that lets me remember the pass through bidirectoral logic for more than 1 day. Removed the interface and replaced it with 3 lines of code.
2016-01-19 13:30:09 -05:00
Andreas Olofsson
3ce9b41726 Working mailbox!
- Gating mailbox_not empty with irq_en. bit [28] of RXCFG
- Changing elink output interrupt to "or" of not_empty and full
- Adding mailbox status register (mostly for debug)
- Moving register addresses to make space for mailbox status register
- Fixing wrappers for DV
- Updating README docs with new register map
- Removing mailbox from RX status reg. Doesn't belong there, should be coupled with mailbox for modularity.
2015-11-29 12:20:17 -05:00
Andreas Olofsson
08f5d28ed4 Test cleanup 2015-11-25 23:49:56 -05:00
Andreas Olofsson
cc362ae72a Fixing DUT
- Adding read response pushback
- Adding random WAIT generation on memory
2015-11-24 09:11:19 -05:00
Andreas Olofsson
57702798e5 Changing testbench to reflect real design
- The axi slave can never drive enough reads to saturate the maxi fifo since it's only sending out one read at a time.
- Changing the system so that a raw elink sits in front of stimulus..
2015-11-18 23:52:10 -05:00
Andreas Olofsson
c8b931efb0 Improving the elink_axi environment
- Turns out there was a bug hidden in the emaxi that can only be found by properly driving a master device with reads. This could not happen in the old environment.
- Note that due to limitations in the esaxi, I had to add the etx_fifo block as an interface (simplest).
- The ESAXI is very limited in that it MUST interface to a fifo with spare entries. (so prog_full). This should be FIXED!
- Minimal test passes, now to try to reproduce the DMA bug..
2015-11-18 23:26:59 -05:00
Andreas Olofsson
8820c8500a Adding wait circuit for axi/elink 2015-11-12 10:47:52 -05:00
Andreas Olofsson
867b750c50 Adding write from stimulus to dv link1
- also, more cleanup of ID parameters
2015-11-11 14:02:02 -05:00
Andreas Olofsson
6dcd5e96bf Cleanup after lock width change for zynq axi 2015-11-09 20:39:16 -05:00
Andreas Olofsson
63bf5d25a4 Moving to active low reset
- Because this is the right thing to do for chips
- Not going to tell you why...
2015-11-06 16:51:57 -05:00
Andreas Olofsson
3969e6d19e Moving to MIT license 2015-11-06 11:25:05 -05:00
Andreas Olofsson
6b83cdb0d7 Testbench bug fix
- can't connect a 64 bit interface to a 32bit one...
- (abuse of emaxi..)
2015-11-03 21:50:26 -05:00
Andreas Olofsson
f849f2410f Adding infrastructure for axi_elink
- Need to clean up some of these files later
2015-11-03 19:52:08 -05:00