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Author SHA1 Message Date
Andreas Olofsson
8c4c730682 added etype to elink instantiation 2015-09-27 08:40:09 -04:00
Andreas Olofsson
531a1fc85a fixing cut off line 2015-09-25 15:42:22 -04:00
Andreas Olofsson
90bd596edc Merge branch 'master' of https://github.com/parallella/oh 2015-09-25 15:41:19 -04:00
Andreas Olofsson
36f9764b07 Linking in clocking diagram 2015-09-25 15:40:52 -04:00
Andreas Olofsson
b0cc7bf006 shrinking diagram even more... 2015-09-25 15:39:26 -04:00
Andreas Olofsson
e965023273 shrinking diagram 2015-09-25 15:36:37 -04:00
Andreas Olofsson
fffac5e4b6 adding clocking png file 2015-09-25 15:25:33 -04:00
Andreas Olofsson
e42443574d Adding clocking diagram 2015-09-25 15:22:12 -04:00
Andreas Olofsson
8b9ddb5d34 Hard coding for ephycard, may need to fix back later... 2015-09-25 15:21:21 -04:00
Andreas Olofsson
22a2443d1e Removed rendundant clock 2015-09-25 15:20:21 -04:00
Andreas Olofsson
cfbbfeb574 Adding "ETYPE" as a parameter 
-set to 0 for parallella
-set to 1 for ephycard
 2015-09-14 22:03:22 -04:00
Andreas Olofsson
58226bc867 Returned erx_io to old format! 
-Burst works again!
-There was definitely a bug on the frame signal, need to pay close attention to all the clock signals, let's review!
 2015-09-14 22:02:16 -04:00
Andreas Olofsson
d7508f9938 DV cleanup 
-Set VCO_MULT to 1 for PLL. Dirty hack to allow the RX clk to phase align with the input. Otherwise, if you multiply the VCO clock and then divide, you get a random phase alignment the way the current clock divider is written.
-Changed the fifo_cdc to 32 entries. Forgot that I had changed the fifo_cdc to hard coded per number of entries. Really need to have a parametrixed model that works!!
 2015-09-14 21:58:52 -04:00
Andreas Olofsson
0415b01753 Clock changes 
-separated PLL and MMCM
-rx clock only on PLL
-removed lock (fix further)
-simplified parameters, more intuitive to change
 2015-09-14 20:25:12 -04:00
Andreas Olofsson
cada5bd9b6 Adding clock tracking on PLL/DLL 
-Fixed PLL model to make it properly phase aligned with CLKIN
 2015-09-14 20:23:25 -04:00
Andreas Olofsson
31f6c94857 Removing random wait for now: 
-the read-after write is annoying
 2015-09-14 20:22:18 -04:00
Andreas Olofsson
31bbb6476b Remving delay from mmu 2015-09-14 13:29:42 -04:00
Andreas Olofsson
23e0f60388 cleanup 2015-09-14 13:28:44 -04:00
Andreas Olofsson
0bfd4d85fc Adding sim parameter 
-lenth of reset pulse should be driven from sim environment
 2015-09-11 18:25:08 -04:00
Andreas Olofsson
c00003e9a3 Changing clocks back: 
-txclk should depend on the sysclk not rxclk
 2015-09-11 18:24:00 -04:00
Andreas Olofsson
090a6c2b1e Fixing interfaces due to moving idelay ctrl to clock block 2015-09-11 12:15:22 -04:00
Andreas Olofsson
52cded4eb2 Fixing Icarus compile error 
-multi dimensional parameters not working
-trying with regs
 2015-09-11 12:08:46 -04:00
Andreas Olofsson
0ec0794bbd Filling in missing parameters 
-needed for Icarus verilog simulator
 2015-09-11 12:08:07 -04:00
Andreas Olofsson
b4fa198ed7 Merge pull request #10 from olajep/patch-1 
README.md: ETX_CFG == 0xF0210
 2015-09-07 15:42:00 -04:00
Ola Jeppsson
efb1eea253 README.md: ETX_CFG == 0xF0210 2015-09-07 19:50:28 +02:00
Andreas Olofsson
012b08a1b6 Merge pull request #9 from plindstroem/master 
Changing receiver clock
 2015-09-01 10:34:01 -04:00
Patrik Lindström
137d8bfdb0 Changing receiver clock 
Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>
 2015-09-01 16:11:52 +02:00
Andreas Olofsson
f753325686 Merge pull request #8 from plindstroem/master 
Receiver fixes
 2015-08-31 10:12:38 -04:00
Patrik Lindström
14beca6a8f Script fixes 
Signed-off-by: Patrik Lindström <patrik.lindstrom@foi.se>
 2015-08-25 18:21:19 +02:00
Patrik Lindström
8f144a050a Script fixes 
Signed-off-by: Patrik Lindström <patrik.lindstrom@foi.se>
 2015-08-25 18:17:30 +02:00
Patrik Lindström
abebbeb7dd Adding xgui 
Signed-off-by: Patrik Lindström <patrik.lindstrom@foi.se>
 2015-08-25 14:58:37 +02:00
Patrik Lindström
a5c160fc0d Script fixes 
Signed-off-by: Patrik Lindström <patrik.lindstrom@foi.se>
 2015-08-25 13:03:44 +02:00
Patrik Lindström
1a642a31d6 Removing ephycard define 
Signed-off-by: Patrik Lindström <patrik.lindstrom@foi.se>
 2015-08-25 12:40:48 +02:00
Patrik Lindström
e598635815 Script fixes 
Signed-off-by: Patrik Lindström <patrik.lindstrom@foi.se>
 2015-08-25 12:36:23 +02:00
Patrik Lindström
5e8b10eafb Bug fixes 
Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>
 2015-08-24 22:50:28 +02:00
Patrik Lindström
98a17d6ccf Changing RX clocking 
Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>
 2015-08-24 22:39:51 +02:00
Patrik Lindström
9d71189f93 Changing the receiver to use both frame signals 
Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>
 2015-08-24 21:39:31 +02:00
Patrik Lindström
f9c2a5abf3 moving idelay controller to eclocks.v 
Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>
 2015-08-24 21:08:49 +02:00
Andreas Olofsson
d81bb66d73 Writing while full is aserted 2015-08-14 17:15:38 -04:00
Andreas Olofsson
9bc40a8355 Fixing wait issue 
-Removing the wait signal from the pipeline
-Assumption is that the prog_full is used on fifo, allowing two entries
to be captured in fifo.
-May revisit this at some time...
 2015-08-14 17:13:52 -04:00
Andreas Olofsson
ede8656081 Fixing mutual exclusive bug on receiver 
-When a read response is detected, there should be no spurious transactions to the RD/WR request fifos.
-Move the "filter" backt to the erx_protocol block
-Removed the remap bypass signal (was hacky)
-Passes simulations again..
 2015-08-14 15:37:37 -04:00
Andreas Olofsson
21686d31cc Reorg for xilinx projects 
-making more modular
-still need to clean up duplucate files
 2015-08-08 12:29:00 -04:00
Andreas Olofsson
b0a321a588 Clarified enable/disable status 
-For now RX/TX is always on
-At some point make default off?
 2015-08-07 09:25:41 -04:00
Andreas Olofsson
8e32299f2c Copyright cleanup 2015-08-07 09:19:37 -04:00
Andreas Olofsson
617e5f76de Updating interface description 2015-08-07 09:15:10 -04:00
Andreas Olofsson
f908acc259 Updating docs 
-clarifications
-removing TX DMA
 2015-08-07 09:09:42 -04:00
Andreas Olofsson
7df92eb1f0 Removing DMA from transmit 
* Seems like a useless feature. Why autogenerate the transactions at the transmit side. This should always be done at the receive side to minimize bits moving across the link.  Can't really see a use for it anymore so I am removing it.
* If you want to hack the design to reduce latency, you can always grab the raw etx_core and drive signals directly through write port.
* May consider adding a fourth port to etx to allow bypassing  the link interfac?
* Add an ifdef to bypass the fifos?
 2015-08-07 09:05:11 -04:00
Andreas Olofsson
5e50d78c51 Merge branch 'master' of https://github.com/parallella/oh 2015-08-07 07:56:44 -04:00
Andreas Olofsson
36e8f78370 README changes and various fixes 2015-08-07 07:56:30 -04:00
Andreas Olofsson
cbc029521b Update README.md 2015-08-04 18:08:02 -04:00