Andreas Olofsson
8d6c07be9b
Changing timeout
...
- Test being cut off too early.
- Really need to implement end of test indication already!!!
2016-01-13 15:32:15 -05:00
Andreas Olofsson
bed1ba5556
Fixing write to TX register bug
...
- The write transaction was incorrectly piped through to axi slave
2016-01-11 20:50:40 -05:00
Andreas Olofsson
fa42bc6e2e
Reset simulation issue
...
- Feels like I have seen this before, but still makes me nervous. The async negedge of reset was never being triggered in simulation by iverilog, probably because the simulation initialized it to 0, so there was no negedge. In logic, this is an async level signal....
2016-01-11 20:47:06 -05:00
Andreas Olofsson
307794711d
Error message in one hot mux
2016-01-11 17:35:15 -05:00
Andreas Olofsson
d1062fbff8
Changing dp memory interface in calling module
2016-01-11 17:34:35 -05:00
Andreas Olofsson
d4c5118a72
Making single/dual port memory interfaces constistant
2016-01-11 15:06:22 -05:00
Andreas Olofsson
4a454d71bd
Making AW main parameter
2016-01-11 15:05:21 -05:00
Andreas Olofsson
1d540e7b49
Adding comments to table
2016-01-10 17:06:08 -05:00
Andreas Olofsson
32522280e6
Cleanup
2016-01-10 15:58:28 -05:00
Andreas Olofsson
c1da2531e6
Formatting
2016-01-10 15:18:40 -05:00
Andreas Olofsson
3168228174
Adding functionality for various modules
...
(Work in progress, not tested)
2016-01-10 13:33:31 -05:00
Andreas Olofsson
d5d315b5b9
Adding missing parameter
2016-01-10 11:59:14 -05:00
Andreas Olofsson
55eeafe0db
Compile cleanup
2016-01-10 11:58:54 -05:00
Andreas Olofsson
0568add03a
Changing emesh stimulus suffix ti "*.emf"
2016-01-10 11:57:38 -05:00
Andreas Olofsson
e9d3c78b17
Adding interfaces
2015-12-17 13:50:59 -05:00
Andreas Olofsson
2672519ab0
Adding memory to driver
...
-More modular, foudn myself adding memories in a lot of places
2015-12-17 12:53:20 -05:00
Andreas Olofsson
ec627556f7
Fixing basic FIFO bug
...
- count was not fully reset...
- adding parameter values to memory instance
2015-12-10 19:32:15 -05:00
Andreas Olofsson
22976b781d
Adding count/almost full to fifo
2015-12-08 21:10:17 -05:00
Andreas Olofsson
dd811ab417
Fixing unconnected wire bug
2015-12-05 09:01:18 -05:00
Andreas Olofsson
2d953d5639
Fixed unconnected wires in standby circuit
2015-12-04 17:32:15 -05:00
Andreas Olofsson
f5bb42dfe3
Moving axi cells to own folder
2015-12-04 03:38:26 -05:00
Andreas Olofsson
d5edb1ca88
Fixing priority on etx_arbiter
...
- don't do a combinatorial loopback on wait in a primitive cell, just bad practice...
- changed priority to give readback priority over read, safer?
2015-12-04 03:36:42 -05:00
Andreas Olofsson
eb8f6c1f51
Adding datagate power saving module
2015-12-03 18:05:08 -05:00
Andreas Olofsson
8464c3dcb0
Adding standby logic block
2015-12-03 18:04:46 -05:00
Andreas Olofsson
16b0655151
Name change for arbiter
2015-12-03 18:04:10 -05:00
Andreas Olofsson
b9107474a9
Vectorizing oh_clockgate
2015-12-03 18:03:02 -05:00
Andreas Olofsson
69d2c2c5fb
Prettyfying csa port names
2015-12-03 18:01:47 -05:00
Andreas Olofsson
3a8f81d4a3
Changing single port memory to be ASIC friendly
2015-12-03 18:01:21 -05:00
Andreas Olofsson
7b8460b145
Fixing up issues with database reorg
...
- Not sure where the prog_full issue popped up from. (sign of disorganized databsae)
-
2015-11-30 15:07:28 -05:00
Andreas Olofsson
19fa611bb9
Massive reorganization to impove reuse
...
- adding more chip code
- pushing memory stuff into common
- making common "oh_" naming class
-
2015-11-30 13:45:49 -05:00
Andreas Olofsson
9ddd71024d
Fixing system_bd interface for "mailbox_irq" signal
2015-11-29 12:41:53 -05:00
Andreas Olofsson
162cb022f9
Adding pushback circuit to stimulus
2015-11-24 01:04:14 -05:00
Andreas Olofsson
074186bd31
Adding new axi utility lib to sim file + README cleanup
2015-11-18 23:33:08 -05:00
Andreas Olofsson
aff0d82a30
Fixing issue with bit stream write
...
- Script was exiting before bit stream was written
2015-11-17 22:13:46 -05:00
Andreas Olofsson
3102d6cd44
Adding comments
2015-11-16 09:58:47 -05:00
Andreas Olofsson
4b384be602
Fixing edge align circuit
...
- duh error
- making output positive edge aligned, the negedge nastyness should be maintained within module...
2015-11-14 23:33:48 -05:00
Andreas Olofsson
e70c51670c
Adding edge align circuit
2015-11-14 22:41:19 -05:00
Andreas Olofsson
75cef84075
Timescale stuff
...
- Need to look into this again, gotchas here
-
2015-11-13 16:25:38 -05:00
Andreas Olofsson
3f1296b099
Cleanup
2015-11-12 10:50:05 -05:00
Andreas Olofsson
a9e034bef9
Bringing access low during wait
2015-11-12 00:58:06 -05:00
Andreas Olofsson
04cd179f5a
Lint fixes for icarus/verilator
2015-11-09 21:57:25 -05:00
Andreas Olofsson
55ba8ff635
Cleaning up warnings from FGPA tools
...
- removing unconnected ports
- only one rst input for async_fifo
- synchronizing the reset input toe emaxi fifo
2015-11-09 13:23:40 -05:00
Andreas Olofsson
cf2123ce88
Don't generate fifo during packaging
2015-11-09 13:22:27 -05:00
Andreas Olofsson
64f55eb792
Fix 0 day bug...
...
- this shows why it's so important to read the warnings. (circuit was broken!)
2015-11-09 13:21:26 -05:00
Andreas Olofsson
01fd24e069
Fixing synchronization reset speed path
...
- This seems silly, why even have a syncrhonizer
- Safe to set speed path?
2015-11-09 00:16:35 -05:00
Andreas Olofsson
875e4213a5
Adding attributes to sync logic
...
- Otherwise tool was throwing away logic and timing incorretly.
- This is why you HAVE to isolate this logic! Solve the problem once for all logic and for everyone.
2015-11-08 23:30:47 -05:00
Andreas Olofsson
b6c95e5b94
Cleanup
2015-11-06 22:34:08 -05:00
Andreas Olofsson
979b20a451
Fixing name on fileset for constraints
...
- Apparantly has to be fixed to constr&^(I&W)%
2015-11-06 22:32:46 -05:00
Andreas Olofsson
ebf2e861de
Need to validate design before writing tcl
2015-11-06 20:47:35 -05:00
Andreas Olofsson
a683e58597
Associating clock with bus interface
...
- This should be moved to the block , block specific...
2015-11-06 20:45:38 -05:00
