- The response time for async fifo was not fast enough due to synchronization, was causing problems when connecting memory/reg directly to output.
- Was found in testbench, but is generally applicable.
- Also simplifying/refactoring names
-adding clock bypass mode for esystx[12]
-removing monitor feature on erx
-remove loopback support from doc
-add clock bypass mode for esysclk
-shortening register names (descriptive enough)
-added debug signal information
-moving registers to elink
-making elink version programmable (to support plug in boards)
-reorganized debug signals and added stickys
-added timeout for axi slave
-removed embox status bit (redudant, don't poll status)
-renamed EMBOX0-->EMBOXLO
-moved datain interface straight to ecfg (cleanup)
-changed etx arbiter priority to increase stability
-created the esaxi_mux block
-fixed some missing ports issues in stubs
Now comes the fun part...verification...
Andreas
-this may break already broken projects
-creates a Verilog top level (instead of using Vivado block level design)
-integrates mmy and mailbox (not completely integrated)
-compiles...
-pours in all of the code from the archive
(some new logic created)
-Each directory contains one sub block
-Each directory contains a dv/docs/hdl directory, self contained.
-May need to add constraints directory as well at some point.
-This is the right thing to do, make each block modular and self contained.
