- reset was broken!
- need to account for wait
- merging read/write wait for simplicity, otherwise you would need to reset the packets to figure out if it's a read or write transaction...and I don't want to reset every packet throughout the pipe.
- holding rx in reset state until tx is done
- removing reset from all pipeline registers
- removing reset from oddr/iddr
- the idea is to keep things quiet not to block in lots of places. The only real block needed is in the FIFO to keep "noise" from propagating past the link. The link should be kept in a safe reset state until the rx fram is stable and the clock is running so that the pipe can be cleaned out.
- Making all resets async since we cannot guarantee that we have a clock coming in from RX. This is needed due to the way we use a PLL for alignment. If we would have used a free running local clock this would have been different, but this would have required a FIFO for synchronization betwen the rx and rxdiv4 clock.
- Moving the clock block into the RX for modularity
- Making a specil rx soft reset (driven from sys_clk domain)
- Still there is a POR_reset so the link should wake up ok
- This is DEFINITELY the way to do things, sweep the delays and find the right value. No f'ing way to get these stupid FPGAs to work otherwise with the ridiculuosly over margined PVT nubmers they are running through the STAs. I understand they want to make the design bullet proof, but as a result designers are wasting countless hours overoptimzinng designs and being clever. So much performance is left on the table for expert users.
- Lesson: I/O design should be "self syncrhonizing". Only contraints in the design should be create_clk
- Made RX clock async, too tricky to guarantee that there clock is there. No way to do this if the clock sources are actually independent for RX/TX!
-Removing the wait signal from the pipeline
-Assumption is that the prog_full is used on fifo, allowing two entries
to be captured in fifo.
-May revisit this at some time...
-When a read response is detected, there should be no spurious transactions to the RD/WR request fifos.
-Move the "filter" backt to the erx_protocol block
-Removed the remap bypass signal (was hacky)
-Passes simulations again..
