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4 Commits

Author SHA1 Message Date
Andreas.Olofsson
84e8449cb5 Moving sampling to negedge for clarity 2020-07-14 13:50:24 -04:00
Andreas.Olofsson
2c106bed5e Moving checker to positive edge 
-This should be synthesizable into FPGAs!
 2020-04-22 23:15:41 -04:00
Andreas.Olofsson
d8d2d0c20e Changing dv_checker to oh_simchecker 
-library consistency
 2020-04-22 22:40:43 -04:00
Andreas.Olofsson
cf47e56436 Changing dv_* to oh_* to be consistent 2020-04-22 21:52:37 -04:00