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1,429 Commits 7 Branches 1 Tag
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63 Commits

Author SHA1 Message Date
Andreas.Olofsson
9ac530e526 Adding indication that test started for regression clarity 2020-07-19 10:12:07 -04:00
Andreas.Olofsson
84e8449cb5 Moving sampling to negedge for clarity 2020-07-14 13:50:24 -04:00
Andreas.Olofsson
58eedb914d Cleanup 2020-04-22 23:17:25 -04:00
Andreas.Olofsson
7c0e1bc01f Adding fail criteria to common simulation control infrastucture 
-Preparing for CI and unit tests for all modules
 2020-04-22 23:16:43 -04:00
Andreas.Olofsson
2c106bed5e Moving checker to positive edge 
-This should be synthesizable into FPGAs!
 2020-04-22 23:15:41 -04:00
Andreas.Olofsson
d8d2d0c20e Changing dv_checker to oh_simchecker 
-library consistency
 2020-04-22 22:40:43 -04:00
Andreas.Olofsson
cf47e56436 Changing dv_* to oh_* to be consistent 2020-04-22 21:52:37 -04:00
Andreas.Olofsson
064ec792d3 Adding testname to simplfy grepping of regression suite results 2020-03-26 12:22:56 -04:00
Andreas.Olofsson
069681ca6a Typo fix in dv_ctrl 2020-02-17 07:43:41 -05:00
Andreas.Olofsson
a09374d74b Adding FAIL timeout condition in test 2020-02-15 21:58:17 -05:00
Andreas.Olofsson
c04523503e Making stimulus configurable 
-ability to turn off timesetamps dynamically
-ability to ignore valid signal
 2020-02-06 12:50:34 -05:00
Andreas.Olofsson
ca3c01144f Changing stimulus order to avoid on memh 2020-02-04 22:42:41 -05:00
Andreas.Olofsson
f7012f8369 Basic memh based stimulus file. 
-Much cleaner than previous work!
-Allows for loading into FPGA!
 2020-02-03 13:19:55 -05:00
Andreas.Olofsson
1bd7c552fb Adding basic tesbench for stimulus function 
-testing the tester
 2020-02-03 13:19:21 -05:00
Andreas.Olofsson
b23a63e2ba Adding firmware example for readmemh 2020-02-03 13:16:37 -05:00
Andreas.Olofsson
e017f0f290 Stimulus write port written 
-Read port half done, looks straight forward
 2020-02-02 23:11:29 -05:00
Andreas.Olofsson
c23862f4a6 Starting general purpose design of stimulus! 
-memory based, generic
 2020-02-02 21:35:15 -05:00
Andreas.Olofsson
7bd980fca2 Adding include directorys to lib.cmd 2020-02-01 09:07:47 -05:00
Andreas.Olofsson
d6f5de24d7 Changing hierarchy to promote blocks 2020-01-28 18:12:57 -05:00
Andreas Olofsson
7094173ae9 Reorg! Why? 
- The top level directory was not scaling, too imposing
- Friendlier to download a repo and see a finite number of top level dirs
- We are just getting started...
 2016-03-22 08:13:40 -04:00
Andreas Olofsson
a6f1dc8971 Merge branch 'master' of github.com:parallella/oh 2016-03-22 08:01:04 -04:00
Andreas Olofsson
85ecd25268 Remving the ugly wait hack in the stimulus, not the way to drive the pipeline 2016-03-21 20:51:35 -04:00
Andreas Olofsson
4d172960c1 Renaming the generic dut template file 2016-03-11 16:40:30 -05:00
Andreas Olofsson
e1f8b1d6c4 Adding dummy dut to make autocomplete work in emacs 2016-03-11 16:38:17 -05:00
Andreas Olofsson
d9f18e7b58 DV cleanup 
-removing all redundant build files, there must be only one...
 2016-03-08 21:23:02 -05:00
Andreas Olofsson
e549a63a04 Reorg/cleanup 2016-03-08 19:37:42 -05:00
Andreas Olofsson
6e22772420 Removed autoinst for dut.v 
-Had to remove the dummy dut.v to make scripts and links cleaner
 2016-03-08 19:36:44 -05:00
Andreas Olofsson
e622aa1b33 Reorg 2016-03-08 15:49:54 -05:00
Andreas Olofsson
274f5f93c6 Renamed C2C to MIO 2016-02-26 22:51:35 -05:00
Andreas Olofsson
a5194a30a3 Reorg 
-Renaming constants files as ".vh"
-Cleanup parameters
 2016-02-26 19:08:40 -05:00
Andreas Olofsson
67afb87881 Cleaning up sp memory changes 
-removing incorrect bist dout port
-repair vector name change
 2016-02-26 17:01:24 -05:00
Andreas Olofsson
cdef6141b4 Adding 2nd clock to interface 
- Randomizeing clock frequencies
- Phase and frequency randomization a must for catching first order sync problems (and debunking really stupid ideas...)
- Don't be clever, be smart!
 2016-02-24 14:23:30 -05:00
Andreas Olofsson
117a4fee0d Doing forall "dut*.v" 
- Adding entries to a list gets old real fast....
 2016-02-24 14:22:32 -05:00
Andreas Olofsson
fc7dc0e70a Adding "SEED" as basic parameter 
-making randomness clocks a first class citizen
-Verilog doesn't have a seed, need to drive it from the shell
-a must for async clocks, useful for many things
-does not preclude randomization externally as well
 2016-02-24 14:21:04 -05:00
Andreas Olofsson
bb4a602f7f New "dut files" 
- new clocks (clk1 and 2)
- simpler names
- fifo dut
 2016-02-24 14:19:57 -05:00
Andreas Olofsson
c9601a8f9c Adding clk90 output to clkdiv 
-Added testbench
-Needs more review!
 2016-02-23 17:49:08 -05:00
Andreas Olofsson
84490be604 Adding testbench for clockdiv and gray converter 2016-02-23 17:17:41 -05:00
Andreas Olofsson
be22598935 Adding basic unit wiggle tests 2016-02-23 17:17:05 -05:00
Andreas Olofsson
8e466f3137 Adding debouncer circuit 2016-02-23 15:41:18 -05:00
Andreas Olofsson
c8b9de9f42 Adding gpio and spi paths 2016-01-24 23:42:06 -05:00
Andreas Olofsson
abd25426b6 Fixing various small bugs 
-sandbox accelerator working in simulation!
-t0+6 hrs wall time (lost 2 hours due to travel)
 2016-01-20 17:23:09 -05:00
Andreas Olofsson
ca5db9fa4d Interface cleanup 
- fifo interface changes
- maxi/saxi name changes
- general code cleanup
- register remapping for mailbox
 2016-01-19 13:33:08 -05:00
Andreas Olofsson
8d6c07be9b Changing timeout 
- Test being cut off too early.
- Really need to implement end of test indication already!!!
 2016-01-13 15:32:15 -05:00
Andreas Olofsson
fa42bc6e2e Reset simulation issue 
- Feels like I have seen this before, but still makes me nervous. The async negedge of reset was never being triggered in simulation by iverilog, probably because the simulation initialized it to 0, so there was no negedge. In logic, this is an async level signal....
 2016-01-11 20:47:06 -05:00
Andreas Olofsson
307794711d Error message in one hot mux 2016-01-11 17:35:15 -05:00
Andreas Olofsson
4a454d71bd Making AW main parameter 2016-01-11 15:05:21 -05:00
Andreas Olofsson
32522280e6 Cleanup 2016-01-10 15:58:28 -05:00
Andreas Olofsson
0568add03a Changing emesh stimulus suffix ti "*.emf" 2016-01-10 11:57:38 -05:00
Andreas Olofsson
2672519ab0 Adding memory to driver 
-More modular, foudn myself adding memories in a lot of places
 2015-12-17 12:53:20 -05:00
Andreas Olofsson
f5bb42dfe3 Moving axi cells to own folder 2015-12-04 03:38:26 -05:00