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Author SHA1 Message Date
Patrik Lindström
6a232d7834 adding project folder 2015-06-30 13:58:20 +02:00
Patrik Lindström
634ff371ac Bug fixes 2015-06-30 13:32:05 +02:00
Patrik Lindström
48fdf2d782 Added iostandard parameter 2015-06-30 12:44:22 +02:00
Patrik Lindström
f232d9d297 Changed rx_ref_clk PLL divider 2015-06-30 12:35:38 +02:00
Patrik Lindström
8c0dbffb61 Added different IDW for m_axi and s_axi 2015-06-30 12:31:14 +02:00
Andreas Olofsson
537bb6a330 Cleanup 2015-06-25 22:14:19 -04:00
Andreas Olofsson
e960b6f7c0 Adding IP package reference script 2015-06-25 22:14:05 -04:00
Andreas Olofsson
fc31ad57fd Reorg 2015-06-25 19:52:28 -04:00
Andreas Olofsson
d9155f6538 Placeholder for elink 2015-06-25 16:17:20 -04:00
Andreas Olofsson
eb7028fdbf Reorg 2015-06-25 16:13:20 -04:00
Andreas Olofsson
badac2aa76 Name changes for signal grouping 2015-06-25 16:09:05 -04:00
Andreas Olofsson
b0c7b75407 Adding OBUF model 2015-06-25 15:42:20 -04:00
Andreas Olofsson
2cbf91b07b Making reset sync in emmu 2015-05-23 22:26:15 -04:00
Andreas Olofsson
7b8a9cf474 Adding IP file for async fifo 
-This is the place for all generic IP blocks
 2015-05-23 22:24:44 -04:00
Andreas Olofsson
bc53400888 Adding parallella block design 
-Start with gui
-Generate block design
-Edit text, this is f'ing crazy!
-If this is the only way to use the vivado IP not sure I want it
-Strive towards doing everything in verilog
-Split into:
1.) Verilog block (no IP!)
2.) One top level to instantiate IP + clean verilog block
-Never fight the tools..
 2015-05-22 21:38:39 -04:00
Andreas Olofsson
c9f64a2fb2 Fixing dv to check axi_elink 
-Need to split these, getting too cumbersome
 2015-05-21 22:56:23 -04:00
Andreas Olofsson
1eb2bcea89 Removing custom xilinx primitives 
-Using the memory_sp macro instead...
-Cleaner design
-axi_elink now works!
 2015-05-21 22:54:29 -04:00
Andreas Olofsson
24d824f080 Fixing read response address 
-using `define from elink_regmap (ie 'D')
 2015-05-20 15:04:29 -04:00
Andreas Olofsson
7f0f858b92 Letting read response packets through 
-Needed for loopback testing
 2015-05-20 15:03:22 -04:00
Andreas Olofsson
a60de7fb30 Adding readback on axi_elink 
-Another cludgy memory
-Note that current esaxi doesn't support pushback so we have to hack the test to avoid read/write contention on this port.
 2015-05-19 23:53:05 -04:00
Andreas Olofsson
b1c3b3fb8c Adding filtering to ecfg_if 
-Avoids garbage writing coming back to esaxi
 2015-05-19 23:52:00 -04:00
Andreas Olofsson
005c9872dd Removing timeout from logic 
-Should be direct interface to esaxi
 2015-05-19 23:51:17 -04:00
Andreas Olofsson
7d524d0f68 Changing axi interface <--> elink protocol 
-Now consistant with packet, access, wait protocol
 2015-05-19 22:08:41 -04:00
Andreas Olofsson
8d3cbf8257 Clean axi_elink module 
-Clocks included inside for easy integration
-Another version might have the clocks and reset as inputs instead
 2015-05-19 22:07:16 -04:00
Andreas Olofsson
6d9731f14a Including environment for axi_elink 
-Should probably split this into separate environments
-Getting bulky and ugly...
 2015-05-19 22:06:15 -04:00
Andreas Olofsson
815db5669e Merge branch 'master' of https://github.com/parallella/oh 2015-05-18 15:39:42 -04:00
Andreas Olofsson
451a1fa925 MILESTONE: Bursts working!!! 
-Fairly clean minimalist design
-Complete redesign
-Need to do random read/write testing to make sure
-Speed?
 2015-05-18 15:38:30 -04:00
Andreas Olofsson
665876cfb4 Adding bursting to test bench 2015-05-18 15:37:46 -04:00
Andreas Olofsson
3ff0d56057 Deleting MIT license for now to avoid confusion. 
Everything is GPL until further notice
 2015-05-18 12:16:17 -04:00
Andreas Olofsson
41f97e45ff Converting to synchronous reset 2015-05-17 23:00:53 -04:00
Andreas Olofsson
ae8d4b4dcd Adding more reports 
-check_timing is a crucial summary
 2015-05-17 22:35:15 -04:00
Andreas Olofsson
559ffcc6e0 File name changes and additions 2015-05-17 22:34:42 -04:00
Andreas Olofsson
6485d1a9e7 Adding input delay constraints for RX 
-doesn't meet timing
-needs work...
 2015-05-17 22:33:42 -04:00
Andreas Olofsson
665af097c6 Name change 
-chip_resetb instead of resetb
 2015-05-17 22:32:39 -04:00
Andreas Olofsson
1ec8991e2a Adding IDELAY elements to xilibs 2015-05-16 22:07:17 -04:00
Andreas Olofsson
4fb6e7407c Integrating idelay elements in erx_io 2015-05-16 22:06:40 -04:00
Andreas Olofsson
017b72c37a MILESTONE: "almost final" block works! 
-bursting disabled, otherwise it looks good!
 2015-05-15 15:32:43 -04:00
Andreas Olofsson
d052da4ec9 Speed optimization 
-adding IDDR/ODDR blocks in IO
-still need to add the IDELAY controller and blocks
 2015-05-15 15:31:01 -04:00
Andreas Olofsson
9d3ecd0d06 Clock block cleanup 
-Moving TXCLK to CCLK domain, "feels cleaner"
-Also makes TXCLK independent of RXCLK
-So complete solution has a PLL and an MMCM
-Feeling is that the PLL for RXCLK could eventually be removed
-Need to add more state for locking clocks for receiver at end?
REVIEW!!!
 2015-05-15 15:28:19 -04:00
Andreas Olofsson
cd624d6531 Adding IDDR model 2015-05-15 15:27:45 -04:00
Andreas Olofsson
1f89e682bb Adding warning regarding clock divider 
-For now only div by 2/4/8 supported
-Really need to implement general purpose integer clock divider!
 2015-05-15 15:26:59 -04:00
Andreas Olofsson
ee363f6119 Fixed ODDR model for SAME_EDGE mode 2015-05-15 09:46:08 -04:00
Andreas Olofsson
836c4a65a8 Adding PLLE2_ADV model 2015-05-14 22:49:42 -04:00
Andreas Olofsson
a2d8c5c453 Adding PLL LOCK functionality 
-not accurate, but at least it gives some dunmy behavior for PLLLOCK
 2015-05-14 22:48:55 -04:00
Andreas Olofsson
02cc0f2b4f Adding reset to both sides of fifo 2015-05-14 22:47:25 -04:00
Andreas Olofsson
2e9744cd44 Changing default to simplify instantiation 2015-05-14 22:46:23 -04:00
Andreas Olofsson
35d86bcdc3 Adding pulse_stretcher circuit 
-simple but powerful for syncing from fast to slow clock domains
 2015-05-14 22:45:32 -04:00
Andreas Olofsson
007797169c Clock and reset interface changes 2015-05-14 22:43:44 -04:00
Andreas Olofsson
d2dcc15c52 Reset and clock cleanup 
-In the default mode we now have 7 input clocks to basic elink
-This is too many, need to simplify, not reasonable!
-But with all the knobs on the MMCM, performance will be great...
-WIP on bursting...
 2015-05-14 22:31:42 -04:00
Andreas Olofsson
77e210e7c2 Synchronous exit from reset 
-Async asert, sync deassert
-Haven't used this before.. (review?)
 2015-05-14 22:28:41 -04:00