Andreas Olofsson
d8b5fa78ef
Adding emesh as basic building block
2015-05-05 21:38:41 -04:00
Andreas Olofsson
d0439f871f
Adding example design for FPGA
2015-05-05 21:37:17 -04:00
Andreas Olofsson
c843fc5fe0
Renaming for my sanity (etx/erx split)
2015-05-05 14:56:35 -04:00
Andreas Olofsson
300e5a14fc
Reorg
2015-05-05 14:47:21 -04:00
Andreas Olofsson
a3cfa17b06
Removing old module
2015-05-04 22:38:28 -04:00
Andreas Olofsson
3e74d68dcc
Both input and output models were wrong.
...
Should match datasheet now...
2015-05-04 22:35:55 -04:00
Andreas Olofsson
de74f8accc
Removed synchronizer, not needed
2015-05-04 22:34:14 -04:00
Andreas Olofsson
b2846c5312
MILESTONE: Read/write works back and forth
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-Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1
-Still not completely happy with reset (using async for now)
2015-05-04 17:13:51 -04:00
Andreas Olofsson
570fbffd7f
Baking in the IO wait signal into rd/wr wait
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-Separate waits for rd/wr wait
-Adding wait to protocol block as well
-io_wait always goes through
-using active frame signal to select/clear data for output
2015-05-04 17:10:32 -04:00
Andreas Olofsson
dcf72537e4
Separate rd/wr stalls
2015-05-04 17:09:50 -04:00
Andreas Olofsson
c3fe37dc90
Separating rd/wr wait for pipeline stall
2015-05-04 17:09:23 -04:00
Andreas Olofsson
ec3dbc910a
Using async reste on fifo output access signal
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-For cases where there is no clock at output
2015-05-04 17:07:55 -04:00
Andreas Olofsson
0aba754b7e
Cleanup
2015-05-04 10:54:42 -04:00
Andreas Olofsson
8b37d29f27
File cleanup
2015-05-04 10:54:23 -04:00
Andreas Olofsson
72aff72558
MILESTONE: register read/write working!
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-Bullet proof clock domain crossings!
2015-05-04 10:49:17 -04:00
Andreas Olofsson
bb8f5f861b
Moving the read response to separate group (not register)
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Why?
1.) This will allow for support of multiple outstanding channels at some point
2.) Much easier to debug, can tag transactions in test bench
2015-05-04 10:41:42 -04:00
Andreas Olofsson
e9d6794833
Blocking TX outgoing transcations on LINKID match
2015-05-04 10:41:14 -04:00
Andreas Olofsson
25b0b188ff
Implementing register readback on read response channel
2015-05-04 10:40:43 -04:00
Andreas Olofsson
6907d39490
Making readback work
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-Simplifying logic for rx_en
-Reaback data was incorrectly pipelined (one too many)
2015-05-04 10:39:01 -04:00
Andreas Olofsson
b63de8b1d8
Filter the txwr access
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We don't want reset/clock transaction to propagate through etx!
2015-05-04 10:37:27 -04:00
Andreas Olofsson
75f653ffd6
Naming cleanup
2015-05-04 10:37:08 -04:00
Andreas Olofsson
b375aaeb07
Adding back emesh access
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-Write from emesh, read from mi.
-Final decision?
-Make readback 64 bits.
2015-05-04 10:36:07 -04:00
Andreas Olofsson
861c690ebb
Adding rd_en to fifo_async
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-Need to hold output when there is no read_access
(important assumption!)
2015-05-04 10:35:23 -04:00
Andreas Olofsson
1ee720fc67
Organization changes
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-dma with packet format
-using the fifo_cdc block
2015-05-03 23:29:32 -04:00
Andreas Olofsson
51b14f41ce
wait in vs. wait out confusion
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wait_out is the signal being driven out telling someone else to wait
wait_in is the incoming signal telling "you" to wait".
2015-05-03 23:26:43 -04:00
Andreas Olofsson
cfe811e7a7
Complete redesign
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-Following access,wait, packet pipeline format
-Use a priority arbiter
2015-05-03 23:25:19 -04:00
Andreas Olofsson
5470c1dc8f
Enable 2 clock operation for EMMU
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The dual port memory should support this in most cases
2015-05-03 23:24:27 -04:00
Andreas Olofsson
47a143eada
Turning on clocks by default (low frequency)
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Seems safer
2015-05-03 23:23:28 -04:00
Andreas Olofsson
2d698266de
Making dma quiet until implemented
2015-05-03 23:23:02 -04:00
Andreas Olofsson
b05f236d13
Clocks on during reset
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-Otherwise we can't do sync reset anywhere
-glitch on exit from reset? Do we care? Everything is static
-Need to check this again!
2015-05-03 23:21:10 -04:00
Andreas Olofsson
21dcedbda2
Adding simple priority arbiter
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Yes it's simple, but youl should never have to rewrite this code
For larger arbiters, too much risk of making a mistake...
Arbitration mistakes aver nasty to find and nasty to debug!
2015-05-03 23:19:40 -04:00
Andreas Olofsson
19e22c38d7
Adding proper wait to fifo_cdc
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If there is a waitm, we should
1.) Not increment the read pointer
2.) Hold the packet steady until wait signal goes away
3.) Hold access high, keep request intact
2015-05-03 23:17:23 -04:00
Andreas Olofsson
781121fc61
Cleanup
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-setting DMA access to zero for now
-taking away wait for elink2 (messes up the access pattern)
-fixing typo in register mape ERX
2015-05-02 23:04:13 -04:00
Andreas Olofsson
2da588721a
Fixed verilog syntax issue
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-Not sure what parameter couldn't be used directly here?
-Works fine when parameter is assigned to wire.
2015-05-02 23:03:14 -04:00
Andreas Olofsson
dcd2d0b111
Clock/reset fixes
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-Making reset async
-lclk_div4 always on (makes reset safer, not a big loss)
-filtering non-matching transactions
2015-05-02 22:42:33 -04:00
Andreas Olofsson
cb9a1f50dd
Fixing ecfg_clocks
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-Was missing clock connection
-Adding ID to match only to the right transcations
2015-05-02 22:40:27 -04:00
Andreas Olofsson
ebd9a89afd
Adding constants to handle model
2015-05-02 21:30:26 -04:00
Andreas Olofsson
56fa70c0dd
Connecting wait output from e16_model
2015-05-02 21:29:43 -04:00
Andreas Olofsson
130caa64b6
E16 model cleanup
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-fixing false error message
-removed emesh_interface isntance (not needed..)
-set floating inputs to zero
2015-05-02 21:28:09 -04:00
Andreas Olofsson
e5fc895a25
Cleanup
2015-05-01 18:33:29 -04:00
Andreas Olofsson
340d99cab1
Instance renaming
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Will help with FPGA synthesis reports (uniqueness needed sometimes)
2015-05-01 18:19:36 -04:00
Andreas Olofsson
8461277ab1
Complete redesign of configuration register file
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-There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect!
-Configuration can be done from host through txwr/txrd path of any register
-The RX IO pins can only access the RX side of the design
2015-05-01 17:58:16 -04:00
Andreas Olofsson
f215e07ce9
Updated to fit new ERX_RR register
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-Read response now returns to a memory mapped register
2015-05-01 17:53:55 -04:00
Andreas Olofsson
23cb2acb31
Updated constants file to fit new register map
2015-05-01 17:52:55 -04:00
Andreas Olofsson
4059a6eaa2
Created unified one clock modular confi for RX/TX
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-Solves clock domain crossing uglyness
-Very nice and clean!!
-Only compromise is that the RESET and CLOCK registers aren't readable
2015-05-01 17:51:12 -04:00
Andreas Olofsson
20534a6ed1
Added testmode to transmitter
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-pin driven testmode driven..b/c fpga designers often don't like software
-and because it's really convenient, press a push button and see a pattern appear
-removed protocol description, goes in README.md, there should only be one source for documentation
-shortened signal names for ecfg
-changed to "clk" input now that everything is single clock
2015-05-01 17:47:24 -04:00
Andreas Olofsson
93f0fb6220
README cleanup
2015-05-01 17:42:12 -04:00
Andreas Olofsson
1c14ccd5d9
Generalizing emailbox
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-There should be two clocks
(even though there is only one clock in erx)
2015-05-01 17:34:04 -04:00
Andreas Olofsson
08b871941d
Adding e16 elink golden reference to dv environment
2015-05-01 17:32:52 -04:00
Andreas Olofsson
0ca303432b
Cleanup
2015-05-01 17:31:45 -04:00
