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7 Commits

Author SHA1 Message Date
Andreas Olofsson
93330039e0 AXI bug fixes
-First bug was a typo. Cursing AXI for making every signal look exactly the same at first glance.  Not good use practice
-Second bug was sloppy. (removed pipeline stage on write data by mistake)
2015-04-14 20:26:58 -04:00
Andreas Olofsson
b9d3c5ac5c Verilator lint cleanup
~10 real bugs
-mostly name mismatches and bit range mistakes
2015-04-14 14:00:23 -04:00
Andreas Olofsson
f33d940df8 Fixed renaming bug..axi ready signal not working
(would have been caught by verilator, time to lint...)
2015-04-14 13:08:27 -04:00
Andreas Olofsson
d809f46286 Removing unused signals from interface 2015-04-14 11:44:31 -04:00
Andreas Olofsson
5bd5d1ff54 Man that's a lot of yak shaving....
-added register read/write properly
-removed redundant wrapper layers in maxi/saxi
-changed over to "emesh" interface from packet 103 bit data
-cleaned up maxi
-cleaned up saxi
-removed redundant signals in elink interface (user,lock,..)
-added wrapper to fifo (to carry emesh interface through)

Now comes the fun part of testing
2015-04-13 23:35:21 -04:00
Andreas Olofsson
d45439b43e Changing emesh/elink transaction order
Our "standard packet" order should be followed everywhere to ease verification and integration (standards are good fir reuse...):
[0]=access
[1]=write
[3:2]=datamode
[7:4]=ctrlmode
[39:8]=dstaddr
[71:40]=data
[103:72]=upper-data (or srcaddr)
2015-04-12 08:59:53 -04:00
Andreas Olofsson
baebdab381 Reorganizing files...too many folders after all.
There is only one elink...
2015-04-11 00:10:16 -04:00