- This is DEFINITELY the way to do things, sweep the delays and find the right value. No f'ing way to get these stupid FPGAs to work otherwise with the ridiculuosly over margined PVT nubmers they are running through the STAs. I understand they want to make the design bullet proof, but as a result designers are wasting countless hours overoptimzinng designs and being clever. So much performance is left on the table for expert users.
- Lesson: I/O design should be "self syncrhonizing". Only contraints in the design should be create_clk
- Made RX clock async, too tricky to guarantee that there clock is there. No way to do this if the clock sources are actually independent for RX/TX!
-apparantly the MMCM needs a reset after the clock changes
-need to hold reset high until we know that there is an active clock on input
-doesn't it make more sense to use idelay?
-Set VCO_MULT to 1 for PLL. Dirty hack to allow the RX clk to phase align with the input. Otherwise, if you multiply the VCO clock and then divide, you get a random phase alignment the way the current clock divider is written.
-Changed the fifo_cdc to 32 entries. Forgot that I had changed the fifo_cdc to hard coded per number of entries. Really need to have a parametrixed model that works!!
-Removing the wait signal from the pipeline
-Assumption is that the prog_full is used on fifo, allowing two entries
to be captured in fifo.
-May revisit this at some time...
-When a read response is detected, there should be no spurious transactions to the RD/WR request fifos.
-Move the "filter" backt to the erx_protocol block
-Removed the remap bypass signal (was hacky)
-Passes simulations again..
* Seems like a useless feature. Why autogenerate the transactions at the transmit side. This should always be done at the receive side to minimize bits moving across the link. Can't really see a use for it anymore so I am removing it.
* If you want to hack the design to reduce latency, you can always grab the raw etx_core and drive signals directly through write port.
* May consider adding a fourth port to etx to allow bypassing the link interfac?
* Add an ifdef to bypass the fifos?
