14 Commits

Author	SHA1	Message	Date
Andreas Olofsson	947a804c62	Making reset async ... - making ecfg_elink reset only depend on por (otherwise chicken and egg) -	2015-10-07 14:46:12 -04:00
Andreas Olofsson	415b8113df	Adding proper "ETYPE" for wait signals ... -single and diff should be fully supported	2015-09-27 08:40:36 -04:00
Andreas Olofsson	8b9ddb5d34	Hard coding for ephycard, may need to fix back later...	2015-09-25 15:21:21 -04:00
Andreas Olofsson	cfbbfeb574	Adding "ETYPE" as a parameter ... -set to 0 for parallella -set to 1 for ephycard	2015-09-14 22:03:22 -04:00
Patrik Lindström	5e8b10eafb	Bug fixes ... Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>	2015-08-24 22:50:28 +02:00
Patrik Lindström	f9c2a5abf3	moving idelay controller to eclocks.v ... Signed-off-by: Patrik Lindström <lindstroeem@gmail.com>	2015-08-24 21:08:49 +02:00
Andreas Olofsson	8e32299f2c	Copyright cleanup	2015-08-07 09:19:37 -04:00
Patrik Lindström	6d13611f21	script fixes	2015-06-30 16:02:39 +02:00
Patrik Lindström	667c7cb6a8	script fixes	2015-06-30 14:56:27 +02:00
Patrik Lindström	48fdf2d782	Added iostandard parameter	2015-06-30 12:44:22 +02:00
Patrik Lindström	8c0dbffb61	Added different IDW for m_axi and s_axi	2015-06-30 12:31:14 +02:00
Andreas Olofsson	badac2aa76	Name changes for signal grouping	2015-06-25 16:09:05 -04:00
Andreas Olofsson	8d3cbf8257	Clean axi_elink module ... -Clocks included inside for easy integration -Another version might have the clocks and reset as inputs instead	2015-05-19 22:07:16 -04:00
Andreas Olofsson	ab26378a99	Adding elink with axi interfaces	2015-05-09 08:52:55 -04:00