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473 Commits 7 Branches 1 Tag
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321 Commits

Author SHA1 Message Date
Andreas Olofsson
befc18f368 MILESTONE: read/write works with all new RX/TX IO logic! 
-Fixes issue with back to back transactions!
-Read/writes work!!
-Needs more verification/analysis...
 2015-05-14 00:00:12 -04:00
Andreas Olofsson
4245c16b0d Adjusting phases for clocks 
-This is because the PLL model does not account for the input clock
-Actually a big dangerous cheat...
-How to model a PLL more accurately?
 2015-05-13 23:57:33 -04:00
Andreas Olofsson
4cd1e36537 Testbench update to include new clocking scheme 2015-05-13 23:30:30 -04:00
Andreas Olofsson
6ba45155fd Integrating clock approach change 
-clocks moved outside elink
-new packet interface format between protocol and io block
 2015-05-13 23:29:18 -04:00
Andreas Olofsson
b8c699fb22 Complete redesign 
-Communication with IO is with "packet format"
-No need to invent a 64 bit format just for stupid OSERDES
 2015-05-13 23:28:06 -04:00
Andreas Olofsson
af1f8a03eb Complete redesign 
-junking the old logic
-not needed with new IO approach
 2015-05-13 23:27:35 -04:00
Andreas Olofsson
0214df5804 Complete redesign of erx io logic 
-Building from primitives
-Work in progress, not quite complete
 2015-05-13 23:26:41 -04:00
Andreas Olofsson
9dcde59979 Complete redesign of erx 
-Giving up on ISERDES. No freaking proper documentaion and no open source simulation model.
-Rewriting io module with primitives.
-Looks like most of the logic disappears...
-Still work in progress
 2015-05-13 23:24:54 -04:00
Andreas Olofsson
89d54f4ed8 More flexible clock solution 
-moving clock block outside elink
-driving all key clocks into erx/etx
 2015-05-13 23:23:23 -04:00
Andreas Olofsson
a03b036b29 Formatting resource table 2015-05-12 08:18:58 -04:00
Andreas Olofsson
169ab2d488 Adding FPGA resource numbers 2015-05-12 08:13:25 -04:00
Andreas Olofsson
36696e709e Updates for new interface 
-shortening to fit new clock
 2015-05-12 07:42:56 -04:00
Andreas Olofsson
624d0e6134 Reorg cleanup 
-renamed disty for consistency (there is an arbiter there now)
-adding missing ID to etx/erx
-New org working!
 2015-05-12 07:41:48 -04:00
Andreas Olofsson
fb96664a9c Fixed width files doesn't work with .md files 2015-05-11 23:45:25 -04:00
Andreas Olofsson
5105790ff0 Adding address next to name 
(ease of use)
 2015-05-11 23:39:32 -04:00
Andreas Olofsson
bb37be52db Updating elink register descritons 
-removing unused features
-updating register names
-updating structure
-simplifying protocol text
 2015-05-11 23:18:21 -04:00
Andreas Olofsson
92fa02c44a Wide image instead of centering.. 2015-05-11 22:45:15 -04:00
Andreas Olofsson
12fd779558 Cropping image 2015-05-11 22:28:46 -04:00
Andreas Olofsson
b5e53f8196 Adding images, rearranging 2015-05-11 22:26:57 -04:00
Andreas Olofsson
a68a094285 Adding elink header image 2015-05-11 22:25:27 -04:00
Andreas Olofsson
3432c5fb45 Adding elink block diagram 2015-05-11 21:27:49 -04:00
Andreas Olofsson
81db0b7582 Completing elink hierarchy change 
-splits out clock domains
-makes the core portion a clean/reusable module with defined interface
 2015-05-10 23:38:08 -04:00
Andreas Olofsson
d2b4dabc58 Moving chipid back to clocks 
-unnatural for it to be in etx
(link has nothing to do with epiphany id)
 2015-05-10 23:35:41 -04:00
Andreas Olofsson
a627ecae7b Removing testmode, bad idea 
-Should be input to fifo or etx_core
 2015-05-10 23:35:04 -04:00
Andreas Olofsson
eaadfc6465 Adding etx/erx core modules 
-Single clock domain
-Super-light...
-Need to be able to remove internal feature as well
-(MMU/DMA should be optional but on by default..)
 2015-05-10 23:06:52 -04:00
Andreas Olofsson
fa374e666a Cleanup 2015-05-09 08:57:49 -04:00
Andreas Olofsson
eb3051ea93 Cleaning up logic to fit new access/packet interface 
(pre-debug)
 2015-05-09 08:56:51 -04:00
Andreas Olofsson
ab26378a99 Adding elink with axi interfaces 2015-05-09 08:52:55 -04:00
Andreas Olofsson
d83efbdb8e Cleaning up initial constraints 
-Now generates bit stream
-It won't work, but it's a start...
 2015-05-08 20:56:33 -04:00
Andreas Olofsson
a52fa86edb Fixing instances errors from fpga synthesis 2015-05-08 20:55:31 -04:00
Andreas Olofsson
9793be3bf0 Fixing crucial error in documentation 
-Nothing worse than incorrect comments!
 2015-05-07 23:52:02 -04:00
Andreas Olofsson
38d7fe1af9 Clock cleanup 
-Moving to single clock
-Unifying the timescale (1ns period)
-Stopping access when done with stimulus file
 2015-05-07 23:46:32 -04:00
Andreas Olofsson
1f6c18a764 Using fifo_cdc instead of fifo_async 2015-05-07 23:45:36 -04:00
Andreas Olofsson
c51f8f3dc9 Adding clock buffer 2015-05-07 23:44:39 -04:00
Andreas Olofsson
773bab5c6a First version of synthesis tcl scripts for elink example 2015-05-07 23:43:05 -04:00
Andreas Olofsson
ba32323306 Cleaning up clocks 
-moving to "real" Xilinx PLL instantiation
-one PLL for CCLK one for LCLK
-removing clock dividers, can't work at speed, put inside model
-configuration needs to be done differently
-removing pll_bypass signal, can't work with logic
-clocks should be done with hard macro primitives (no logic)
 2015-05-06 12:23:15 -04:00
Andreas Olofsson
4f487d498e Making simulation more "real" 
-Working with timescale (for viewer mostly)
-Now using TARGET_XILINX as default in sim
 2015-05-06 12:21:39 -04:00
Andreas Olofsson
d8b5fa78ef Adding emesh as basic building block 2015-05-05 21:38:41 -04:00
Andreas Olofsson
d0439f871f Adding example design for FPGA 2015-05-05 21:37:17 -04:00
Andreas Olofsson
c843fc5fe0 Renaming for my sanity (etx/erx split) 2015-05-05 14:56:35 -04:00
Andreas Olofsson
300e5a14fc Reorg 2015-05-05 14:47:21 -04:00
Andreas Olofsson
a3cfa17b06 Removing old module 2015-05-04 22:38:28 -04:00
Andreas Olofsson
de74f8accc Removed synchronizer, not needed 2015-05-04 22:34:14 -04:00
Andreas Olofsson
b2846c5312 MILESTONE: Read/write works back and forth 
-Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1
-Still not completely happy with reset (using async for now)
 2015-05-04 17:13:51 -04:00
Andreas Olofsson
570fbffd7f Baking in the IO wait signal into rd/wr wait 
-Separate waits for rd/wr wait
-Adding wait to protocol block as well
-io_wait always goes through
-using active frame signal to select/clear data for output
 2015-05-04 17:10:32 -04:00
Andreas Olofsson
dcf72537e4 Separate rd/wr stalls 2015-05-04 17:09:50 -04:00
Andreas Olofsson
0aba754b7e Cleanup 2015-05-04 10:54:42 -04:00
Andreas Olofsson
72aff72558 MILESTONE: register read/write working! 
-Bullet proof clock domain crossings!
 2015-05-04 10:49:17 -04:00
Andreas Olofsson
bb8f5f861b Moving the read response to separate group (not register) 
Why?
1.) This will allow for support of multiple outstanding channels at some point
2.) Much easier to debug, can tag transactions in test bench
 2015-05-04 10:41:42 -04:00
Andreas Olofsson
e9d6794833 Blocking TX outgoing transcations on LINKID match 2015-05-04 10:41:14 -04:00