Andreas Olofsson
25b0b188ff
Implementing register readback on read response channel
2015-05-04 10:40:43 -04:00
Andreas Olofsson
6907d39490
Making readback work
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-Simplifying logic for rx_en
-Reaback data was incorrectly pipelined (one too many)
2015-05-04 10:39:01 -04:00
Andreas Olofsson
b63de8b1d8
Filter the txwr access
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We don't want reset/clock transaction to propagate through etx!
2015-05-04 10:37:27 -04:00
Andreas Olofsson
1ee720fc67
Organization changes
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-dma with packet format
-using the fifo_cdc block
2015-05-03 23:29:32 -04:00
Andreas Olofsson
51b14f41ce
wait in vs. wait out confusion
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wait_out is the signal being driven out telling someone else to wait
wait_in is the incoming signal telling "you" to wait".
2015-05-03 23:26:43 -04:00
Andreas Olofsson
cfe811e7a7
Complete redesign
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-Following access,wait, packet pipeline format
-Use a priority arbiter
2015-05-03 23:25:19 -04:00
Andreas Olofsson
47a143eada
Turning on clocks by default (low frequency)
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Seems safer
2015-05-03 23:23:28 -04:00
Andreas Olofsson
781121fc61
Cleanup
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-setting DMA access to zero for now
-taking away wait for elink2 (messes up the access pattern)
-fixing typo in register mape ERX
2015-05-02 23:04:13 -04:00
Andreas Olofsson
2da588721a
Fixed verilog syntax issue
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-Not sure what parameter couldn't be used directly here?
-Works fine when parameter is assigned to wire.
2015-05-02 23:03:14 -04:00
Andreas Olofsson
dcd2d0b111
Clock/reset fixes
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-Making reset async
-lclk_div4 always on (makes reset safer, not a big loss)
-filtering non-matching transactions
2015-05-02 22:42:33 -04:00
Andreas Olofsson
cb9a1f50dd
Fixing ecfg_clocks
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-Was missing clock connection
-Adding ID to match only to the right transcations
2015-05-02 22:40:27 -04:00
Andreas Olofsson
ebd9a89afd
Adding constants to handle model
2015-05-02 21:30:26 -04:00
Andreas Olofsson
56fa70c0dd
Connecting wait output from e16_model
2015-05-02 21:29:43 -04:00
Andreas Olofsson
130caa64b6
E16 model cleanup
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-fixing false error message
-removed emesh_interface isntance (not needed..)
-set floating inputs to zero
2015-05-02 21:28:09 -04:00
Andreas Olofsson
e5fc895a25
Cleanup
2015-05-01 18:33:29 -04:00
Andreas Olofsson
340d99cab1
Instance renaming
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Will help with FPGA synthesis reports (uniqueness needed sometimes)
2015-05-01 18:19:36 -04:00
Andreas Olofsson
8461277ab1
Complete redesign of configuration register file
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-There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect!
-Configuration can be done from host through txwr/txrd path of any register
-The RX IO pins can only access the RX side of the design
2015-05-01 17:58:16 -04:00
Andreas Olofsson
f215e07ce9
Updated to fit new ERX_RR register
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-Read response now returns to a memory mapped register
2015-05-01 17:53:55 -04:00
Andreas Olofsson
23cb2acb31
Updated constants file to fit new register map
2015-05-01 17:52:55 -04:00
Andreas Olofsson
4059a6eaa2
Created unified one clock modular confi for RX/TX
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-Solves clock domain crossing uglyness
-Very nice and clean!!
-Only compromise is that the RESET and CLOCK registers aren't readable
2015-05-01 17:51:12 -04:00
Andreas Olofsson
20534a6ed1
Added testmode to transmitter
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-pin driven testmode driven..b/c fpga designers often don't like software
-and because it's really convenient, press a push button and see a pattern appear
-removed protocol description, goes in README.md, there should only be one source for documentation
-shortened signal names for ecfg
-changed to "clk" input now that everything is single clock
2015-05-01 17:47:24 -04:00
Andreas Olofsson
93f0fb6220
README cleanup
2015-05-01 17:42:12 -04:00
Andreas Olofsson
08b871941d
Adding e16 elink golden reference to dv environment
2015-05-01 17:32:52 -04:00
Andreas Olofsson
0ca303432b
Cleanup
2015-05-01 17:31:45 -04:00
Andreas Olofsson
800dacdff4
Updated register map and interface
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-Changed DMA descriptor locations
-Changed colid/rowid -->chipd[11:0] (more consistant)
-Added access column (R/W)
2015-05-01 17:27:24 -04:00
Andreas Olofsson
e168bd5f98
reorg
2015-05-01 17:21:45 -04:00
Andreas Olofsson
0762b90fef
Reorg
2015-05-01 17:21:21 -04:00
Andreas Olofsson
d541a261a6
Adding Epiphany16 elink RTL implementation as reference
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This is pretty big, wonder if anybody will notice?
Why am I doing this?
Because the elink has been haunting us for years. This way we will finally have a "golden reference" simulator model for those who insist on designing their own elink protocol (aginst my recommendation). This is equivalent to having a "bfm-bus functional model" for AXI. The spec is nice, but it's always up for interpretation. We have had some issues with documenting the protocol corretly. While we will fix the documentation, please note that the source code and design verification environment will always be the golden version. This is after all "the silicon".
For me and everyone else, it becomes part of the open source design verification environment to test the elink.
Enjoy....
2015-05-01 17:14:50 -04:00
Andreas Olofsson
5f15ed220d
Changing name
2015-05-01 14:42:15 -04:00
Andreas Olofsson
ad401d09e0
??
2015-04-30 23:35:01 -04:00
Andreas Olofsson
49bcc348e4
Making register map look more like Epiphany
2015-04-30 23:33:00 -04:00
Andreas Olofsson
395a1b3cb7
Merge branch 'master' of https://github.com/parallella/oh
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Adding complete register documentation
Conflicts:
elink/README.md
2015-04-29 11:55:01 -04:00
Andreas Olofsson
2ee3c7d942
merging local readme
2015-04-29 09:27:15 -04:00
Andreas Olofsson
861f5818d2
Updated with new registers and protocol
2015-04-29 09:24:47 -04:00
Andreas Olofsson
3ef05ad63a
Register map twiddling..
2015-04-28 17:00:17 -04:00
Andreas Olofsson
d00d58d116
Read response now a readable memory mapped register
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Much better...hidden addresses SUCK!
2015-04-28 16:58:45 -04:00
Andreas Olofsson
2460aa9247
Bypass erx remap on all ID matches
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Not just for read responses..
2015-04-28 16:58:05 -04:00
Andreas Olofsson
a6ac9b4666
Added bit to etx_remap
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-To enable writing to ERX, we need to include the group number
-support groups F,E,D,C (bits [19:18])
2015-04-28 16:56:31 -04:00
Andreas Olofsson
4ae2c1ecbf
MILESTONE! Working test with new memory map and 2 link system
2015-04-28 16:55:57 -04:00
Andreas Olofsson
6b2d479692
DV environment cleanup
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-removed floating signals
-blocking ID transactions from reaching memory (should be done in real design as well)
2015-04-28 16:55:12 -04:00
Andreas Olofsson
a2ceb8ff6e
Cleanup, two-link environment working
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-Write to config registers from RX path now working
2015-04-28 00:47:26 -04:00
Andreas Olofsson
02812c03a8
Fixing bug on 64 bit register write
2015-04-28 00:46:40 -04:00
Andreas Olofsson
67a05c9363
Fixing floating wait signal bug
2015-04-28 00:46:03 -04:00
Andreas Olofsson
0431d79992
Enabling RX always
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-Should we ever turn this off?
2015-04-28 00:45:16 -04:00
Andreas Olofsson
96c35c4908
Removing filter for rxwr_access
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-Needed to enable simple mi_write interface on RX
2015-04-28 00:44:20 -04:00
Andreas Olofsson
f544c44a08
Adding register access from RX
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-Access without symmetry was awkward, now we can reach regs from TX or RX side
-Removes a special path for mailbox (came for free)
-At the same time reduced clock complexity (one clock for system!!)
-Moved mailbox to top level
-Changed main clock to "sys_clk" for all
2015-04-27 23:51:00 -04:00
Andreas Olofsson
e1a295998f
Adding 2nd elink to dv env
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-The single link env wasn't giving enough coverage
-This is also preparing for inserting the chip reference model...
2015-04-27 23:45:43 -04:00
Andreas Olofsson
6b108f5e1f
Adding reset to synchronizer
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(cause there may not be a clock...)
2015-04-27 16:03:57 -04:00
Andreas Olofsson
df53a2dc4f
Adding missing reset
2015-04-27 16:03:12 -04:00
Andreas Olofsson
a1722b7ae6
Adding timeout circuit
2015-04-27 16:02:15 -04:00
