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Author SHA1 Message Date
Andreas Olofsson
9d3ecd0d06 Clock block cleanup 
-Moving TXCLK to CCLK domain, "feels cleaner"
-Also makes TXCLK independent of RXCLK
-So complete solution has a PLL and an MMCM
-Feeling is that the PLL for RXCLK could eventually be removed
-Need to add more state for locking clocks for receiver at end?
REVIEW!!!
 2015-05-15 15:28:19 -04:00
Andreas Olofsson
cd624d6531 Adding IDDR model 2015-05-15 15:27:45 -04:00
Andreas Olofsson
1f89e682bb Adding warning regarding clock divider 
-For now only div by 2/4/8 supported
-Really need to implement general purpose integer clock divider!
 2015-05-15 15:26:59 -04:00
Andreas Olofsson
ee363f6119 Fixed ODDR model for SAME_EDGE mode 2015-05-15 09:46:08 -04:00
Andreas Olofsson
836c4a65a8 Adding PLLE2_ADV model 2015-05-14 22:49:42 -04:00
Andreas Olofsson
a2d8c5c453 Adding PLL LOCK functionality 
-not accurate, but at least it gives some dunmy behavior for PLLLOCK
 2015-05-14 22:48:55 -04:00
Andreas Olofsson
02cc0f2b4f Adding reset to both sides of fifo 2015-05-14 22:47:25 -04:00
Andreas Olofsson
2e9744cd44 Changing default to simplify instantiation 2015-05-14 22:46:23 -04:00
Andreas Olofsson
35d86bcdc3 Adding pulse_stretcher circuit 
-simple but powerful for syncing from fast to slow clock domains
 2015-05-14 22:45:32 -04:00
Andreas Olofsson
007797169c Clock and reset interface changes 2015-05-14 22:43:44 -04:00
Andreas Olofsson
d2dcc15c52 Reset and clock cleanup 
-In the default mode we now have 7 input clocks to basic elink
-This is too many, need to simplify, not reasonable!
-But with all the knobs on the MMCM, performance will be great...
-WIP on bursting...
 2015-05-14 22:31:42 -04:00
Andreas Olofsson
77e210e7c2 Synchronous exit from reset 
-Async asert, sync deassert
-Haven't used this before.. (review?)
 2015-05-14 22:28:41 -04:00
Andreas Olofsson
d3d8f3f759 Clock and reset integration 
-moving clock and reset outside basic elink
-adding idelay reference clock
-separate and synchronized reset for each domain
-adding proper reset to fifo_cdc  (per domain, not asynch)
 2015-05-14 22:26:05 -04:00
Andreas Olofsson
1d848fe1d5 Making 2015-05-14 22:24:42 -04:00
Andreas Olofsson
5c690d38a1 Adding reset hardware state machine 
-concept developed by Gunnar Hillerstrom (VHDL)
-takes the driver out of the picture
-some people will run this bare metal
-more deterministic
-cuts down on hw/sw development issues
 2015-05-14 22:22:33 -04:00
Andreas Olofsson
a094f835c9 Rename (clarity) 
-file contains chip id, reset, and clocks
-base config driven by sys_clk
 2015-05-14 22:21:05 -04:00
Andreas Olofsson
befc18f368 MILESTONE: read/write works with all new RX/TX IO logic! 
-Fixes issue with back to back transactions!
-Read/writes work!!
-Needs more verification/analysis...
 2015-05-14 00:00:12 -04:00
Andreas Olofsson
4245c16b0d Adjusting phases for clocks 
-This is because the PLL model does not account for the input clock
-Actually a big dangerous cheat...
-How to model a PLL more accurately?
 2015-05-13 23:57:33 -04:00
Andreas Olofsson
58aeb0ee87 Adding warning message to ISERDES/OSERDES 
-Don't use them!!
 2015-05-13 23:33:26 -04:00
Andreas Olofsson
ade946ce90 Updating with new (and correct) modeling 2015-05-13 23:31:52 -04:00
Andreas Olofsson
4cd1e36537 Testbench update to include new clocking scheme 2015-05-13 23:30:30 -04:00
Andreas Olofsson
6ba45155fd Integrating clock approach change 
-clocks moved outside elink
-new packet interface format between protocol and io block
 2015-05-13 23:29:18 -04:00
Andreas Olofsson
b8c699fb22 Complete redesign 
-Communication with IO is with "packet format"
-No need to invent a 64 bit format just for stupid OSERDES
 2015-05-13 23:28:06 -04:00
Andreas Olofsson
af1f8a03eb Complete redesign 
-junking the old logic
-not needed with new IO approach
 2015-05-13 23:27:35 -04:00
Andreas Olofsson
0214df5804 Complete redesign of erx io logic 
-Building from primitives
-Work in progress, not quite complete
 2015-05-13 23:26:41 -04:00
Andreas Olofsson
9dcde59979 Complete redesign of erx 
-Giving up on ISERDES. No freaking proper documentaion and no open source simulation model.
-Rewriting io module with primitives.
-Looks like most of the logic disappears...
-Still work in progress
 2015-05-13 23:24:54 -04:00
Andreas Olofsson
89d54f4ed8 More flexible clock solution 
-moving clock block outside elink
-driving all key clocks into erx/etx
 2015-05-13 23:23:23 -04:00
Andreas Olofsson
a03b036b29 Formatting resource table 2015-05-12 08:18:58 -04:00
Andreas Olofsson
169ab2d488 Adding FPGA resource numbers 2015-05-12 08:13:25 -04:00
Andreas Olofsson
36696e709e Updates for new interface 
-shortening to fit new clock
 2015-05-12 07:42:56 -04:00
Andreas Olofsson
624d0e6134 Reorg cleanup 
-renamed disty for consistency (there is an arbiter there now)
-adding missing ID to etx/erx
-New org working!
 2015-05-12 07:41:48 -04:00
Andreas Olofsson
fb96664a9c Fixed width files doesn't work with .md files 2015-05-11 23:45:25 -04:00
Andreas Olofsson
5105790ff0 Adding address next to name 
(ease of use)
 2015-05-11 23:39:32 -04:00
Andreas Olofsson
bb37be52db Updating elink register descritons 
-removing unused features
-updating register names
-updating structure
-simplifying protocol text
 2015-05-11 23:18:21 -04:00
Andreas Olofsson
92fa02c44a Wide image instead of centering.. 2015-05-11 22:45:15 -04:00
Andreas Olofsson
12fd779558 Cropping image 2015-05-11 22:28:46 -04:00
Andreas Olofsson
b5e53f8196 Adding images, rearranging 2015-05-11 22:26:57 -04:00
Andreas Olofsson
a68a094285 Adding elink header image 2015-05-11 22:25:27 -04:00
Andreas Olofsson
3432c5fb45 Adding elink block diagram 2015-05-11 21:27:49 -04:00
Andreas Olofsson
81db0b7582 Completing elink hierarchy change 
-splits out clock domains
-makes the core portion a clean/reusable module with defined interface
 2015-05-10 23:38:08 -04:00
Andreas Olofsson
d2b4dabc58 Moving chipid back to clocks 
-unnatural for it to be in etx
(link has nothing to do with epiphany id)
 2015-05-10 23:35:41 -04:00
Andreas Olofsson
a627ecae7b Removing testmode, bad idea 
-Should be input to fifo or etx_core
 2015-05-10 23:35:04 -04:00
Andreas Olofsson
eaadfc6465 Adding etx/erx core modules 
-Single clock domain
-Super-light...
-Need to be able to remove internal feature as well
-(MMU/DMA should be optional but on by default..)
 2015-05-10 23:06:52 -04:00
Andreas Olofsson
fa374e666a Cleanup 2015-05-09 08:57:49 -04:00
Andreas Olofsson
eb3051ea93 Cleaning up logic to fit new access/packet interface 
(pre-debug)
 2015-05-09 08:56:51 -04:00
Andreas Olofsson
ab26378a99 Adding elink with axi interfaces 2015-05-09 08:52:55 -04:00
Andreas Olofsson
d83efbdb8e Cleaning up initial constraints 
-Now generates bit stream
-It won't work, but it's a start...
 2015-05-08 20:56:33 -04:00
Andreas Olofsson
a52fa86edb Fixing instances errors from fpga synthesis 2015-05-08 20:55:31 -04:00
Andreas Olofsson
9793be3bf0 Fixing crucial error in documentation 
-Nothing worse than incorrect comments!
 2015-05-07 23:52:02 -04:00
Andreas Olofsson
b2b7f96e86 Making FIFO/memories easier to use 
-WIDTH/DEPTH parameters
-Removing references to "clean" in ifdefs
 2015-05-07 23:50:34 -04:00