Andreas Olofsson
24afa3c9a0
Deleting old files
2015-11-12 11:00:23 -05:00
Andreas Olofsson
4bd164bae4
Giving up..adding fifo generator model from xilinx
2015-11-12 00:55:01 -05:00
Andreas Olofsson
00c7aa6dcf
Fixing model bug for prog_full
...
-I really need to fix this properly...
2015-11-11 22:35:03 -05:00
Andreas Olofsson
fa5011937c
Taking away prog_full from wr_en
...
- The point of prog_full is to give us some slack..
2015-11-11 22:32:21 -05:00
Andreas Olofsson
bf614a9873
Cleaning up fifo interface
...
- removing redundant signals
- configuring to put synchronizer inside fifo
- one reset only (not two)
2015-11-09 13:20:46 -05:00
Andreas Olofsson
63bf5d25a4
Moving to active low reset
...
- Because this is the right thing to do for chips
- Not going to tell you why...
2015-11-06 16:51:57 -05:00
Andreas Olofsson
3969e6d19e
Moving to MIT license
2015-11-06 11:25:05 -05:00
Andreas Olofsson
8b2974feae
Massive reorg!
...
- flattening hierarchy
- removing junk
2015-11-06 10:59:22 -05:00
Andreas Olofsson
e47fd56a21
Bulk edits (clean up later)
2015-11-06 07:03:28 -05:00
Andreas Olofsson
49bf52374d
Changing model to use parameter rather than tick-define
2015-11-04 20:01:31 -05:00
Andreas Olofsson
dbff2623c1
Cleanup
2015-11-04 19:18:45 -05:00
Andreas Olofsson
0cf23a8d1b
Reorg
2015-11-04 19:16:50 -05:00
Andreas Olofsson
81b71df54e
Reorg
2015-11-04 19:15:05 -05:00
Andreas Olofsson
a3b0d9b75c
Fixing pushback bug
...
* Fixed pushback bug at fifo (DUH!)
* Need to verify random pushback at all tx/rx ports
2015-11-02 16:16:10 -05:00
Andreas Olofsson
f42b34ea3c
Moving back to async reset
2015-10-07 19:21:04 -04:00
Andreas Olofsson
d81bb66d73
Writing while full is aserted
2015-08-14 17:15:38 -04:00
Andreas Olofsson
c627827a6b
Fifo cleanup
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-Adding model (one source..)
-generate for 104x32 for xilinx
-making prog_full the default full indicator
-bringing out almost_full for future use
-fixing interface change in all modules
2015-07-02 16:59:38 -04:00
Patrik Lindström
a284dff462
Bug fixes
2015-06-30 14:04:16 +02:00
Patrik Lindström
634ff371ac
Bug fixes
2015-06-30 13:32:05 +02:00
Andreas Olofsson
1eb2bcea89
Removing custom xilinx primitives
...
-Using the memory_sp macro instead...
-Cleaner design
-axi_elink now works!
2015-05-21 22:54:29 -04:00
Andreas Olofsson
02cc0f2b4f
Adding reset to both sides of fifo
2015-05-14 22:47:25 -04:00
Andreas Olofsson
b2b7f96e86
Making FIFO/memories easier to use
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-WIDTH/DEPTH parameters
-Removing references to "clean" in ifdefs
2015-05-07 23:50:34 -04:00
Andreas Olofsson
ec3dbc910a
Using async reste on fifo output access signal
...
-For cases where there is no clock at output
2015-05-04 17:07:55 -04:00
Andreas Olofsson
8b37d29f27
File cleanup
2015-05-04 10:54:23 -04:00
Andreas Olofsson
75f653ffd6
Naming cleanup
2015-05-04 10:37:08 -04:00
Andreas Olofsson
861c690ebb
Adding rd_en to fifo_async
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-Need to hold output when there is no read_access
(important assumption!)
2015-05-04 10:35:23 -04:00
Andreas Olofsson
19e22c38d7
Adding proper wait to fifo_cdc
...
If there is a waitm, we should
1.) Not increment the read pointer
2.) Hold the packet steady until wait signal goes away
3.) Hold access high, keep request intact
2015-05-03 23:17:23 -04:00
Andreas Olofsson
8461277ab1
Complete redesign of configuration register file
...
-There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect!
-Configuration can be done from host through txwr/txrd path of any register
-The RX IO pins can only access the RX side of the design
2015-05-01 17:58:16 -04:00
Andreas Olofsson
a58c2d5279
Adding clock domain crossing module for emesh
...
-Generic, built for reuse
2015-05-01 17:13:44 -04:00
Andreas Olofsson
754aae749f
Adding various helper modules
2015-05-01 17:13:21 -04:00
Andreas Olofsson
2e6130fd19
Adding valid signal to fifo
...
-Since data has one pipeline delay, this makes it much easier to use
-Matches better with Xilinx fifo generator
2015-04-27 11:15:06 -04:00
Andreas Olofsson
79467583c9
Made reset async (there may not be a clock..)
2015-04-24 17:32:17 -04:00
Andreas Olofsson
5ac06cd772
Fixed stupid typos on full/empty
...
Surprised it wasn't caught during iverilog compile
2015-04-23 18:56:49 -04:00
Andreas Olofsson
34813035bc
Changing FIFO interface
...
More inline with standard Xilinx fifo
names, names, names..ugh
2015-04-23 17:53:22 -04:00
Andreas Olofsson
c01a9fbd27
Adding basic readme files
2015-04-21 21:49:40 -04:00
Andreas Olofsson
7685e297fb
Rename
2015-04-21 17:12:52 -04:00
Andreas Olofsson
046294778c
Wrong port direction on output
2015-04-21 17:10:22 -04:00
Andreas Olofsson
e033e233d0
Integrating emesh memory module
...
-This will flush out the final read response path
2015-04-20 23:07:13 -04:00
Andreas Olofsson
6a6f953986
Adding emesh memory module (empty for now)
2015-04-20 23:06:49 -04:00
Andreas Olofsson
7e44dfc84c
Memory read bug (clk floating)
2015-04-19 21:54:22 -04:00
Andreas Olofsson
f606fc5794
Adding high level single ported memory
2015-04-18 16:11:21 -04:00
Andreas Olofsson
c41a0a8640
Cleaning up licenses for consistency
...
-All files still GPLv3
-Placed at the bottom of the file (I am tired of looking at them!)
2015-04-17 22:21:08 -04:00
Andreas Olofsson
7bc3b662ab
Added profull HACK to async_fifo
...
-this module needs rework
-needs to have same capabilities as standard FPGA async fifos
-remove this later
2015-04-17 15:49:58 -04:00
Andreas Olofsson
846bfa3357
Fixing startup issues in transmit path:
...
-adding reset signals to synchronizer to solve startup issues
-setting config in test bench for speedup, default reg config now correct
-fix (my) stupid bug in etx_arbiter
-adding reset to fifo (todo: review this!)
-reviewing "all red" from waveforms is a must. Red (x) on data is ok, but leaving them on control signals is asking for trouble. Better safe than sorry when it comes to reset.
2015-04-15 16:33:20 -04:00
Andreas Olofsson
69f3df4140
Continued work to create clean design:
...
-pll bypass for clocks (customer request)
-adding dividers on all clocks (tx/cclk)
-adding reset block (clearer)
-using commong clock_divider block
-need to clean up divider block later today, slightly broken:-)
2015-04-15 11:54:43 -04:00
Andreas Olofsson
bee90fcacc
Support files for fifo
2015-04-14 23:56:59 -04:00
Andreas Olofsson
4fd4c8e989
Adding platform agnostic dual ported memory and async fifo
2015-04-14 23:56:00 -04:00
Andreas Olofsson
b9d3c5ac5c
Verilator lint cleanup
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~10 real bugs
-mostly name mismatches and bit range mistakes
2015-04-14 14:00:23 -04:00
Andreas Olofsson
b4c5ef302b
Adding fifo wrapper
2015-04-14 09:06:08 -04:00
Andreas Olofsson
239ca128c2
Vivado run through
...
-missed connections
-mismatched bus widths
-missing IP blocks
-cleanup
-proper DV starts tomorrow
2015-04-08 23:40:16 -04:00
