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385 Commits 7 Branches 1 Tag
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183 Commits

Author SHA1 Message Date
Patrik Lindström
a284dff462 Bug fixes 2015-06-30 14:04:16 +02:00
Patrik Lindström
634ff371ac Bug fixes 2015-06-30 13:32:05 +02:00
Patrik Lindström
48fdf2d782 Added iostandard parameter 2015-06-30 12:44:22 +02:00
Patrik Lindström
f232d9d297 Changed rx_ref_clk PLL divider 2015-06-30 12:35:38 +02:00
Patrik Lindström
8c0dbffb61 Added different IDW for m_axi and s_axi 2015-06-30 12:31:14 +02:00
Andreas Olofsson
537bb6a330 Cleanup 2015-06-25 22:14:19 -04:00
Andreas Olofsson
badac2aa76 Name changes for signal grouping 2015-06-25 16:09:05 -04:00
Andreas Olofsson
24d824f080 Fixing read response address 
-using `define from elink_regmap (ie 'D')
 2015-05-20 15:04:29 -04:00
Andreas Olofsson
7f0f858b92 Letting read response packets through 
-Needed for loopback testing
 2015-05-20 15:03:22 -04:00
Andreas Olofsson
b1c3b3fb8c Adding filtering to ecfg_if 
-Avoids garbage writing coming back to esaxi
 2015-05-19 23:52:00 -04:00
Andreas Olofsson
005c9872dd Removing timeout from logic 
-Should be direct interface to esaxi
 2015-05-19 23:51:17 -04:00
Andreas Olofsson
7d524d0f68 Changing axi interface <--> elink protocol 
-Now consistant with packet, access, wait protocol
 2015-05-19 22:08:41 -04:00
Andreas Olofsson
8d3cbf8257 Clean axi_elink module 
-Clocks included inside for easy integration
-Another version might have the clocks and reset as inputs instead
 2015-05-19 22:07:16 -04:00
Andreas Olofsson
451a1fa925 MILESTONE: Bursts working!!! 
-Fairly clean minimalist design
-Complete redesign
-Need to do random read/write testing to make sure
-Speed?
 2015-05-18 15:38:30 -04:00
Andreas Olofsson
41f97e45ff Converting to synchronous reset 2015-05-17 23:00:53 -04:00
Andreas Olofsson
4fb6e7407c Integrating idelay elements in erx_io 2015-05-16 22:06:40 -04:00
Andreas Olofsson
017b72c37a MILESTONE: "almost final" block works! 
-bursting disabled, otherwise it looks good!
 2015-05-15 15:32:43 -04:00
Andreas Olofsson
d052da4ec9 Speed optimization 
-adding IDDR/ODDR blocks in IO
-still need to add the IDELAY controller and blocks
 2015-05-15 15:31:01 -04:00
Andreas Olofsson
9d3ecd0d06 Clock block cleanup 
-Moving TXCLK to CCLK domain, "feels cleaner"
-Also makes TXCLK independent of RXCLK
-So complete solution has a PLL and an MMCM
-Feeling is that the PLL for RXCLK could eventually be removed
-Need to add more state for locking clocks for receiver at end?
REVIEW!!!
 2015-05-15 15:28:19 -04:00
Andreas Olofsson
d2dcc15c52 Reset and clock cleanup 
-In the default mode we now have 7 input clocks to basic elink
-This is too many, need to simplify, not reasonable!
-But with all the knobs on the MMCM, performance will be great...
-WIP on bursting...
 2015-05-14 22:31:42 -04:00
Andreas Olofsson
77e210e7c2 Synchronous exit from reset 
-Async asert, sync deassert
-Haven't used this before.. (review?)
 2015-05-14 22:28:41 -04:00
Andreas Olofsson
d3d8f3f759 Clock and reset integration 
-moving clock and reset outside basic elink
-adding idelay reference clock
-separate and synchronized reset for each domain
-adding proper reset to fifo_cdc  (per domain, not asynch)
 2015-05-14 22:26:05 -04:00
Andreas Olofsson
1d848fe1d5 Making 2015-05-14 22:24:42 -04:00
Andreas Olofsson
5c690d38a1 Adding reset hardware state machine 
-concept developed by Gunnar Hillerstrom (VHDL)
-takes the driver out of the picture
-some people will run this bare metal
-more deterministic
-cuts down on hw/sw development issues
 2015-05-14 22:22:33 -04:00
Andreas Olofsson
a094f835c9 Rename (clarity) 
-file contains chip id, reset, and clocks
-base config driven by sys_clk
 2015-05-14 22:21:05 -04:00
Andreas Olofsson
befc18f368 MILESTONE: read/write works with all new RX/TX IO logic! 
-Fixes issue with back to back transactions!
-Read/writes work!!
-Needs more verification/analysis...
 2015-05-14 00:00:12 -04:00
Andreas Olofsson
4245c16b0d Adjusting phases for clocks 
-This is because the PLL model does not account for the input clock
-Actually a big dangerous cheat...
-How to model a PLL more accurately?
 2015-05-13 23:57:33 -04:00
Andreas Olofsson
6ba45155fd Integrating clock approach change 
-clocks moved outside elink
-new packet interface format between protocol and io block
 2015-05-13 23:29:18 -04:00
Andreas Olofsson
b8c699fb22 Complete redesign 
-Communication with IO is with "packet format"
-No need to invent a 64 bit format just for stupid OSERDES
 2015-05-13 23:28:06 -04:00
Andreas Olofsson
af1f8a03eb Complete redesign 
-junking the old logic
-not needed with new IO approach
 2015-05-13 23:27:35 -04:00
Andreas Olofsson
0214df5804 Complete redesign of erx io logic 
-Building from primitives
-Work in progress, not quite complete
 2015-05-13 23:26:41 -04:00
Andreas Olofsson
9dcde59979 Complete redesign of erx 
-Giving up on ISERDES. No freaking proper documentaion and no open source simulation model.
-Rewriting io module with primitives.
-Looks like most of the logic disappears...
-Still work in progress
 2015-05-13 23:24:54 -04:00
Andreas Olofsson
89d54f4ed8 More flexible clock solution 
-moving clock block outside elink
-driving all key clocks into erx/etx
 2015-05-13 23:23:23 -04:00
Andreas Olofsson
624d0e6134 Reorg cleanup 
-renamed disty for consistency (there is an arbiter there now)
-adding missing ID to etx/erx
-New org working!
 2015-05-12 07:41:48 -04:00
Andreas Olofsson
81db0b7582 Completing elink hierarchy change 
-splits out clock domains
-makes the core portion a clean/reusable module with defined interface
 2015-05-10 23:38:08 -04:00
Andreas Olofsson
d2b4dabc58 Moving chipid back to clocks 
-unnatural for it to be in etx
(link has nothing to do with epiphany id)
 2015-05-10 23:35:41 -04:00
Andreas Olofsson
a627ecae7b Removing testmode, bad idea 
-Should be input to fifo or etx_core
 2015-05-10 23:35:04 -04:00
Andreas Olofsson
eaadfc6465 Adding etx/erx core modules 
-Single clock domain
-Super-light...
-Need to be able to remove internal feature as well
-(MMU/DMA should be optional but on by default..)
 2015-05-10 23:06:52 -04:00
Andreas Olofsson
fa374e666a Cleanup 2015-05-09 08:57:49 -04:00
Andreas Olofsson
eb3051ea93 Cleaning up logic to fit new access/packet interface 
(pre-debug)
 2015-05-09 08:56:51 -04:00
Andreas Olofsson
ab26378a99 Adding elink with axi interfaces 2015-05-09 08:52:55 -04:00
Andreas Olofsson
a52fa86edb Fixing instances errors from fpga synthesis 2015-05-08 20:55:31 -04:00
Andreas Olofsson
1f6c18a764 Using fifo_cdc instead of fifo_async 2015-05-07 23:45:36 -04:00
Andreas Olofsson
c51f8f3dc9 Adding clock buffer 2015-05-07 23:44:39 -04:00
Andreas Olofsson
ba32323306 Cleaning up clocks 
-moving to "real" Xilinx PLL instantiation
-one PLL for CCLK one for LCLK
-removing clock dividers, can't work at speed, put inside model
-configuration needs to be done differently
-removing pll_bypass signal, can't work with logic
-clocks should be done with hard macro primitives (no logic)
 2015-05-06 12:23:15 -04:00
Andreas Olofsson
d8b5fa78ef Adding emesh as basic building block 2015-05-05 21:38:41 -04:00
Andreas Olofsson
d0439f871f Adding example design for FPGA 2015-05-05 21:37:17 -04:00
Andreas Olofsson
c843fc5fe0 Renaming for my sanity (etx/erx split) 2015-05-05 14:56:35 -04:00
Andreas Olofsson
a3cfa17b06 Removing old module 2015-05-04 22:38:28 -04:00
Andreas Olofsson
de74f8accc Removed synchronizer, not needed 2015-05-04 22:34:14 -04:00