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299 Commits 7 Branches 1 Tag
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64 Commits

Author SHA1 Message Date
Andreas Olofsson
38d7fe1af9 Clock cleanup 
-Moving to single clock
-Unifying the timescale (1ns period)
-Stopping access when done with stimulus file
 2015-05-07 23:46:32 -04:00
Andreas Olofsson
4f487d498e Making simulation more "real" 
-Working with timescale (for viewer mostly)
-Now using TARGET_XILINX as default in sim
 2015-05-06 12:21:39 -04:00
Andreas Olofsson
d8b5fa78ef Adding emesh as basic building block 2015-05-05 21:38:41 -04:00
Andreas Olofsson
d0439f871f Adding example design for FPGA 2015-05-05 21:37:17 -04:00
Andreas Olofsson
b2846c5312 MILESTONE: Read/write works back and forth 
-Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1
-Still not completely happy with reset (using async for now)
 2015-05-04 17:13:51 -04:00
Andreas Olofsson
72aff72558 MILESTONE: register read/write working! 
-Bullet proof clock domain crossings!
 2015-05-04 10:49:17 -04:00
Andreas Olofsson
56fa70c0dd Connecting wait output from e16_model 2015-05-02 21:29:43 -04:00
Andreas Olofsson
130caa64b6 E16 model cleanup 
-fixing false error message
-removed emesh_interface isntance (not needed..)
-set floating inputs to zero
 2015-05-02 21:28:09 -04:00
Andreas Olofsson
08b871941d Adding e16 elink golden reference to dv environment 2015-05-01 17:32:52 -04:00
Andreas Olofsson
d541a261a6 Adding Epiphany16 elink RTL implementation as reference 
This is pretty big, wonder if anybody will notice?

Why am I doing this?

Because the elink has been haunting us for years. This way we will finally have a "golden reference" simulator model for those who insist on designing their own elink protocol (aginst my recommendation). This is equivalent to having a "bfm-bus functional model" for AXI. The spec is nice, but it's always up for interpretation. We have had some issues with documenting the protocol corretly. While we will fix the documentation, please note that the source code and design verification environment will always be the golden version. This is after all "the silicon".

For me and everyone else, it becomes part of the open source design verification environment to test the elink.

Enjoy....
 2015-05-01 17:14:50 -04:00
Andreas Olofsson
395a1b3cb7 Merge branch 'master' of https://github.com/parallella/oh 
Adding complete register documentation

Conflicts:
	elink/README.md
 2015-04-29 11:55:01 -04:00
Andreas Olofsson
4ae2c1ecbf MILESTONE! Working test with new memory map and 2 link system 2015-04-28 16:55:57 -04:00
Andreas Olofsson
6b2d479692 DV environment cleanup 
-removed floating signals
-blocking ID transactions from reaching memory  (should be done in real design as well)
 2015-04-28 16:55:12 -04:00
Andreas Olofsson
a2ceb8ff6e Cleanup, two-link environment working 
-Write to config registers from RX path now working
 2015-04-28 00:47:26 -04:00
Andreas Olofsson
67a05c9363 Fixing floating wait signal bug 2015-04-28 00:46:03 -04:00
Andreas Olofsson
e1a295998f Adding 2nd elink to dv env 
-The single link env wasn't giving enough coverage
-This is also preparing for inserting the chip reference model...
 2015-04-27 23:45:43 -04:00
Andreas Olofsson
c9124f415b Added "timeout" to elink interface 
-Use as error interrupt?
-Is there another method for checking error?
 2015-04-27 15:11:56 -04:00
Andreas Olofsson
d0c4e4f3bd Fixing arbitration issue 
-Read/write can collide, adding wait pushback for read
 2015-04-27 11:14:26 -04:00
Andreas Olofsson
3567805823 Adding dummy vector to testbench 
-All zeroes is ignored by stimulus
-Easy to remember...
 2015-04-27 11:13:53 -04:00
Andreas Olofsson
d44ea5d089 Adding monitor for ememory in dv_elink.v 
-Dumps into emem.trace
 2015-04-27 00:06:04 -04:00
Andreas Olofsson
919a5fa5e8 Register map twiddles 
-Fixed test to correspond to new map
 2015-04-25 07:09:52 -04:00
Andreas Olofsson
c0d8c967c4 Address remapping integration 
Integrated remapping logic (compiles)
Starting debug tomorrow...
 2015-04-24 17:39:05 -04:00
Andreas Olofsson
3b637e55f0 MILESTONE: Design once again passes test 
New features:
DMA
MAILBOX directly in RX path
TXMMU
 2015-04-23 23:16:03 -04:00
Andreas Olofsson
5af7a745b1 Created separate IDs for RX and TX 
-We want to make the two directions as separate as possible so no shared variables. Still need a tag for differentiating between write and read response. In addition we need a group to keep the rr separate from mailbox write.
git diffgit c
 2015-04-23 23:10:27 -04:00
Andreas Olofsson
74fe62e94d Broken testbench connections 2015-04-23 20:04:03 -04:00
Andreas Olofsson
0f0ff55928 Verilator based lint cleanup 2015-04-23 18:57:55 -04:00
Andreas Olofsson
155f6a9401 File cleanup 2015-04-23 18:10:07 -04:00
Andreas Olofsson
ec68dddd99 Packet interface changes 2015-04-23 18:09:16 -04:00
Andreas Olofsson
617214cc90 Cleanup 2015-04-22 13:56:29 -04:00
Andreas Olofsson
ba8f400a37 oops 2015-04-21 21:50:03 -04:00
Andreas Olofsson
c01a9fbd27 Adding basic readme files 2015-04-21 21:49:40 -04:00
Andreas Olofsson
275264c84d Reorg 2015-04-21 21:33:49 -04:00
Andreas Olofsson
035b3c9ba5 Milestone: WRITE AND READ FROM HOST WORKS! 2015-04-21 17:16:20 -04:00
Andreas Olofsson
b89d6222d8 Adding test for readback from host 2015-04-21 17:15:56 -04:00
Andreas Olofsson
fc3926ceb1 Added wait signal for reads 2015-04-21 17:13:53 -04:00
Andreas Olofsson
e033e233d0 Integrating emesh memory module 
-This will flush out the final read response path
 2015-04-20 23:07:13 -04:00
Andreas Olofsson
4c44c59079 Message box working... 
-More testing needed!
 2015-04-19 21:55:07 -04:00
Andreas Olofsson
6cc5d6de90 MMU working... 
-Needs more testing
 2015-04-19 21:36:47 -04:00
Andreas Olofsson
7c93c565e9 Adding back awid, arid, lock to AXI interface 2015-04-18 17:35:22 -04:00
Andreas Olofsson
44a4d0e669 Adding gtkwave signals file 2015-04-18 16:42:34 -04:00
Andreas Olofsson
643ceed432 Adding manual test feature to testbench 
-This is as far as I go with fufu testing (random next)
-Add basic test for cleaning up reads/writes
-104 bit packet format for driving transactions, very useful
 2015-04-18 16:14:53 -04:00
Andreas Olofsson
80bb50703b Adding basic elink read/write test 2015-04-18 16:12:04 -04:00
Andreas Olofsson
4c06e4be61 Changed stimulus format to 32b_32b_32b_8b 
Format is:

srcaddr_data_dstaddr_{ctrlmode,datamode,write,access}
 2015-04-17 16:02:23 -04:00
Andreas Olofsson
08a31cd971 MILESTONE: Open souce simulation elink loopback working! 2015-04-17 15:51:55 -04:00
Andreas Olofsson
bd90cc8f92 Fixed testbench bug (copy paste, RX not enabled)... 2015-04-17 10:08:17 -04:00
Andreas Olofsson
dca611c5ba Getting all the clk config numbers aligned 
Not changing these again!!
 2015-04-16 22:48:31 -04:00
Andreas Olofsson
068d63279b Changing ESYSCLK definition (again.....) 
old implementation felt too "cutsy"
this makes for a cleaner usage model (simple shift with param)
also splitting out enable but, not making the CTIMER mistake again
 2015-04-16 22:31:36 -04:00
Andreas Olofsson
b1a9f502ca Xilinx models 
-adding ODDR model
-configuring the ecfg (rx/tx/clk) in testbench
 2015-04-15 17:54:19 -04:00
Andreas Olofsson
846bfa3357 Fixing startup issues in transmit path: 
-adding reset signals to synchronizer to solve startup issues
-setting config in test bench for speedup, default reg config now correct
-fix (my) stupid bug in etx_arbiter
-adding reset to fifo (todo: review this!)
-reviewing "all red" from waveforms is a must. Red (x) on data is ok, but leaving them on control signals is asking for trouble. Better safe than sorry when it comes to reset.
 2015-04-15 16:33:20 -04:00
Andreas Olofsson
69f3df4140 Continued work to create clean design: 
-pll bypass for clocks (customer request)
-adding dividers on all clocks (tx/cclk)
-adding reset block (clearer)
-using commong clock_divider block
-need to clean up divider block later today, slightly broken:-)
 2015-04-15 11:54:43 -04:00