Andreas Olofsson
b3c0cdc082
Adding generic N:1 mux
2016-01-20 17:22:05 -05:00
Andreas Olofsson
1b6f1ecaef
Interface cleanups
2016-01-20 10:51:57 -05:00
Andreas Olofsson
21ac7b690d
Adding rd_counter to sync fifo interface
2016-01-20 10:50:00 -05:00
Andreas Olofsson
b26255dfb5
Fixing weird clog2 error in Vivado
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-I guess you can't use built in function with localparam?
2016-01-19 14:07:04 -05:00
Andreas Olofsson
a270ade1cd
Cleaning up FIFO interfaces
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-making sync/async interfaces more uniform
-removing valid signal, useless...
-preparing for count output
2016-01-19 13:28:47 -05:00
Andreas Olofsson
26a1304405
Fixing silly compiler errors
2016-01-17 21:15:28 -05:00
Andreas Olofsson
a1e19e0a5b
Adding time to debug message
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- Very useful, should add these to all muxes!
2016-01-16 14:43:14 -05:00
Andreas Olofsson
bed1ba5556
Fixing write to TX register bug
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- The write transaction was incorrectly piped through to axi slave
2016-01-11 20:50:40 -05:00
Andreas Olofsson
307794711d
Error message in one hot mux
2016-01-11 17:35:15 -05:00
Andreas Olofsson
d1062fbff8
Changing dp memory interface in calling module
2016-01-11 17:34:35 -05:00
Andreas Olofsson
d4c5118a72
Making single/dual port memory interfaces constistant
2016-01-11 15:06:22 -05:00
Andreas Olofsson
32522280e6
Cleanup
2016-01-10 15:58:28 -05:00
Andreas Olofsson
3168228174
Adding functionality for various modules
...
(Work in progress, not tested)
2016-01-10 13:33:31 -05:00
Andreas Olofsson
d5d315b5b9
Adding missing parameter
2016-01-10 11:59:14 -05:00
Andreas Olofsson
55eeafe0db
Compile cleanup
2016-01-10 11:58:54 -05:00
Andreas Olofsson
e9d3c78b17
Adding interfaces
2015-12-17 13:50:59 -05:00
Andreas Olofsson
ec627556f7
Fixing basic FIFO bug
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- count was not fully reset...
- adding parameter values to memory instance
2015-12-10 19:32:15 -05:00
Andreas Olofsson
22976b781d
Adding count/almost full to fifo
2015-12-08 21:10:17 -05:00
Andreas Olofsson
dd811ab417
Fixing unconnected wire bug
2015-12-05 09:01:18 -05:00
Andreas Olofsson
2d953d5639
Fixed unconnected wires in standby circuit
2015-12-04 17:32:15 -05:00
Andreas Olofsson
d5edb1ca88
Fixing priority on etx_arbiter
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- don't do a combinatorial loopback on wait in a primitive cell, just bad practice...
- changed priority to give readback priority over read, safer?
2015-12-04 03:36:42 -05:00
Andreas Olofsson
eb8f6c1f51
Adding datagate power saving module
2015-12-03 18:05:08 -05:00
Andreas Olofsson
8464c3dcb0
Adding standby logic block
2015-12-03 18:04:46 -05:00
Andreas Olofsson
16b0655151
Name change for arbiter
2015-12-03 18:04:10 -05:00
Andreas Olofsson
b9107474a9
Vectorizing oh_clockgate
2015-12-03 18:03:02 -05:00
Andreas Olofsson
69d2c2c5fb
Prettyfying csa port names
2015-12-03 18:01:47 -05:00
Andreas Olofsson
3a8f81d4a3
Changing single port memory to be ASIC friendly
2015-12-03 18:01:21 -05:00
Andreas Olofsson
7b8460b145
Fixing up issues with database reorg
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- Not sure where the prog_full issue popped up from. (sign of disorganized databsae)
-
2015-11-30 15:07:28 -05:00
Andreas Olofsson
19fa611bb9
Massive reorganization to impove reuse
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- adding more chip code
- pushing memory stuff into common
- making common "oh_" naming class
-
2015-11-30 13:45:49 -05:00
Andreas Olofsson
3102d6cd44
Adding comments
2015-11-16 09:58:47 -05:00
Andreas Olofsson
4b384be602
Fixing edge align circuit
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- duh error
- making output positive edge aligned, the negedge nastyness should be maintained within module...
2015-11-14 23:33:48 -05:00
Andreas Olofsson
e70c51670c
Adding edge align circuit
2015-11-14 22:41:19 -05:00
Andreas Olofsson
55ba8ff635
Cleaning up warnings from FGPA tools
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- removing unconnected ports
- only one rst input for async_fifo
- synchronizing the reset input toe emaxi fifo
2015-11-09 13:23:40 -05:00
Andreas Olofsson
64f55eb792
Fix 0 day bug...
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- this shows why it's so important to read the warnings. (circuit was broken!)
2015-11-09 13:21:26 -05:00
Andreas Olofsson
875e4213a5
Adding attributes to sync logic
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- Otherwise tool was throwing away logic and timing incorretly.
- This is why you HAVE to isolate this logic! Solve the problem once for all logic and for everyone.
2015-11-08 23:30:47 -05:00
Andreas Olofsson
b6c95e5b94
Cleanup
2015-11-06 22:34:08 -05:00
Andreas Olofsson
322dc1119c
Adding standard modules for reset and data sync
2015-11-06 16:51:35 -05:00
Andreas Olofsson
3969e6d19e
Moving to MIT license
2015-11-06 11:25:05 -05:00
Andreas Olofsson
63e0017275
Stimulus end of test issue
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- Still not 100% on this...but test passes
- Teset was hanging even though stim_done went high. Ticks not advancing, pointing towards comb loop, but what is different at end of test?
- Now to test read/writes of registers from axi and set the idelay registers
2015-11-03 19:56:27 -05:00
Andreas Olofsson
85cc46567a
Removing reset
2015-10-08 10:45:27 -04:00
Andreas Olofsson
2e9744cd44
Changing default to simplify instantiation
2015-05-14 22:46:23 -04:00
Andreas Olofsson
35d86bcdc3
Adding pulse_stretcher circuit
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-simple but powerful for syncing from fast to slow clock domains
2015-05-14 22:45:32 -04:00
Andreas Olofsson
61de7c366a
Cleaning up clock divider
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-moving 90 degree phase shift to PLL
2015-05-06 12:26:07 -04:00
Andreas Olofsson
b05f236d13
Clocks on during reset
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-Otherwise we can't do sync reset anywhere
-glitch on exit from reset? Do we care? Everything is static
-Need to check this again!
2015-05-03 23:21:10 -04:00
Andreas Olofsson
21dcedbda2
Adding simple priority arbiter
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Yes it's simple, but youl should never have to rewrite this code
For larger arbiters, too much risk of making a mistake...
Arbitration mistakes aver nasty to find and nasty to debug!
2015-05-03 23:19:40 -04:00
Andreas Olofsson
754aae749f
Adding various helper modules
2015-05-01 17:13:21 -04:00
Andreas Olofsson
0f0ff55928
Verilator based lint cleanup
2015-04-23 18:57:55 -04:00
Andreas Olofsson
2b22d1c4af
Adding emesh to packet converters
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-getting tired of all the typing after all....
2015-04-22 16:43:52 -04:00
Andreas Olofsson
8adc060bc8
Clock divider fixup
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-changed to latest and hopefully final register config
-fixed functional bugs (was broken..)
-added xor for sensing change of clock frequency
2015-04-18 16:12:43 -04:00
Andreas Olofsson
dca611c5ba
Getting all the clk config numbers aligned
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Not changing these again!!
2015-04-16 22:48:31 -04:00
