11 Commits

Author	SHA1	Message	Date
Andreas Olofsson	6e93d0399a	Hold hack.. ... -This needs to be resolved! Currently there is a simulation problem with the PLL and IDDR circuit, likely due to the clock divider. Amazingly enough the circuit works in sim and FPGA, but there was some redundant logic hiding this. -Need to take a closer look at this to get the non-blocking/blocking right in PLL and CLKDIV	2016-01-19 16:01:15 -05:00
Andreas Olofsson	19fa611bb9	Massive reorganization to impove reuse ... - adding more chip code - pushing memory stuff into common - making common "oh_" naming class -	2015-11-30 13:45:49 -05:00
Andreas Olofsson	0fc4b6188a	Test cleanup ... - added lint script using verilator - adding verilator filter commands for fifo behavioral - Longer pushbacks in ememory	2015-11-28 20:15:06 -05:00
Andreas Olofsson	75cef84075	Timescale stuff ... - Need to look into this again, gotchas here -	2015-11-13 16:25:38 -05:00
Andreas Olofsson	04cd179f5a	Lint fixes for icarus/verilator	2015-11-09 21:57:25 -05:00
Andreas Olofsson	75c9c9deb5	Implemented model for IDELAY	2015-11-03 10:32:56 -05:00
Andreas Olofsson	8c9fea0362	Adding async reset behavior	2015-10-07 19:17:59 -04:00
Andreas Olofsson	ad41b25e42	Making reset async	2015-10-07 12:04:15 -04:00
Andreas Olofsson	394920a1e7	Addding phase delay tracking ... - As a dirty a model hack as they come, using positive and negative edge of CLKIN to sample the signal and phase align the clock output. - Will only work with div 2/4/8 etc - There may be other issues, have to think about it... - But the test now passes cleanly and the clocks look good.	2015-09-30 13:40:11 -04:00
Andreas Olofsson	cada5bd9b6	Adding clock tracking on PLL/DLL ... -Fixed PLL model to make it properly phase aligned with CLKIN	2015-09-14 20:23:25 -04:00
Andreas Olofsson	836c4a65a8	Adding PLLE2_ADV model	2015-05-14 22:49:42 -04:00