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5 Commits

Author SHA1 Message Date
Andreas Olofsson
b0b9315bf1 Massive checkin...
-this may break already broken projects
-creates a Verilog top level (instead of using Vivado block level design)
-integrates mmy and mailbox (not completely integrated)
-compiles...
-pours in all of the code from the archive
(some new logic created)
2015-03-24 20:44:03 -04:00
aolofsson
bb39314399 Verious silly compilation fixes, nothing to see here.. 2014-12-14 22:24:16 -05:00
aolofsson
b997ddd691 Adding readback indicator for AXI slave mux 2014-11-06 12:14:49 -05:00
aolofsson
2851e01228 Changed to 20 bit address width for clarity in FPGA block 2014-11-05 19:37:25 -05:00
aolofsson
4ab49e07c2 Reorganizing structure to be IP centric
-Each directory contains one sub block
-Each directory contains a dv/docs/hdl directory, self contained.
-May need to add constraints directory as well at some point.
-This is the right thing to do, make each block modular and self contained.
2014-11-05 14:31:05 -05:00