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Author SHA1 Message Date
Andreas Olofsson
b26255dfb5 Fixing weird clog2 error in Vivado 
-I guess you can't use built in function with localparam?
 2016-01-19 14:07:04 -05:00
Andreas Olofsson
017d15660c Adding Verilog quick reference 2016-01-19 13:40:46 -05:00
Andreas Olofsson
ca5db9fa4d Interface cleanup 
- fifo interface changes
- maxi/saxi name changes
- general code cleanup
- register remapping for mailbox
 2016-01-19 13:33:08 -05:00
Andreas Olofsson
1a7a76e190 Removing filter logic for ID match (bug fix) 
- This was moved to arbiter block
 2016-01-19 13:32:26 -05:00
Andreas Olofsson
e8794b780c Simplifying axi_elink testbench 
- Too much junk in there, couldn't understand my own logic 4 weeks later...
- emesh_if is a disaster, I have yet to find a way to write code that lets me remember the pass through bidirectoral logic for more than 1 day. Removed the interface and replaced it with 3 lines of code.
 2016-01-19 13:30:09 -05:00
Andreas Olofsson
a270ade1cd Cleaning up FIFO interfaces 
-making sync/async interfaces more uniform
-removing valid signal, useless...
-preparing for count output
 2016-01-19 13:28:47 -05:00
Andreas Olofsson
ce7c89ce1e Fixing read response logic 
- Should only pass back read response EGROUP_RR
- Otherwise there would be a match on writing to MAILBOX
 2016-01-19 13:27:22 -05:00
Andreas Olofsson
8852b8db99 Changing timeout value 
-timeout was hit in sim, 8bits is too short
-refactoring to simplify names, rx/tx was confusing
 2016-01-19 13:26:42 -05:00
Andreas Olofsson
0964fae184 Changing to sync fifo 
- The response time for async fifo was not fast enough due to synchronization, was causing problems when connecting memory/reg directly to output.
- Was found in testbench, but is generally applicable.
- Also simplifying/refactoring names
 2016-01-19 13:25:19 -05:00
Andreas Olofsson
ce26571cec Adding aes block 2016-01-17 21:26:34 -05:00
Andreas Olofsson
26a1304405 Fixing silly compiler errors 2016-01-17 21:15:28 -05:00
Andreas Olofsson
2fb37bdc12 Removing archive directory 2016-01-16 15:15:09 -05:00
Andreas Olofsson
240e5b433c Moving mailbox registers to new addres 
-Mailbox is a pretty useful little block, registers don't belong in the RX space
-Moved registers to the "MESH" group block at bits [10:8].
-Feel good about this, should not change...
-Has been tested  to work with test/test_regs.emf
-For new register address, see README.md

cc @olajep @peteasa
 2016-01-16 14:44:35 -05:00
Andreas Olofsson
a1e19e0a5b Adding time to debug message 
- Very useful, should add these to all muxes!
 2016-01-16 14:43:14 -05:00
Andreas Olofsson
0bcab09269 Cleaning up unused constants 2016-01-16 14:42:57 -05:00
Andreas Olofsson
cece4ce3ac Fixing warning/cleanup 
- port widths don't match for ctrlmode
 2016-01-15 18:14:29 -05:00
Andreas Olofsson
5b37e2c658 Merge pull request #33 from olajep/emaxi-fix 
axi/hdl/emaxi: Fix signal names
 2016-01-15 17:14:35 -05:00
Ola Jeppsson
80b9a88c3c axi/hdl/emaxi: Fix signal names 
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
 2016-01-14 21:21:55 +01:00
Andreas Olofsson
cd17b8130d Adding support for 64core board 2016-01-13 15:32:46 -05:00
Andreas Olofsson
8d6c07be9b Changing timeout 
- Test being cut off too early.
- Really need to implement end of test indication already!!!
 2016-01-13 15:32:15 -05:00
Andreas Olofsson
c6bf2e2bb9 Removing "bid" parameter from emmu 
-Access signal decoded from outside
 2016-01-13 15:31:38 -05:00
Andreas Olofsson
6f6413eddc Updated regs test 2016-01-13 15:30:37 -05:00
Andreas Olofsson
b5179a097d Cleanup 2016-01-13 15:30:15 -05:00
Andreas Olofsson
17431aefa0 Initial commit of open verilog reference 
-Work in progress!!!
 2016-01-12 09:11:15 -05:00
Andreas Olofsson
b56da83aeb Clarifying R/W permissions on some registers 2016-01-12 09:02:37 -05:00
Andreas Olofsson
57c44bafb1 Fixing MMU write access 
- MMU was being written when it shouldn't
 2016-01-12 09:02:00 -05:00
Andreas Olofsson
804edcbc67 Adding reset signal to burst 2016-01-12 09:00:36 -05:00
Andreas Olofsson
f283b87e9d Adding elink_monitor 
- Burst not supported
 2016-01-12 08:38:45 -05:00
Andreas Olofsson
2bbe1e11b1 Change to TXCFG register! 
- Made room for extra bit in ctrlmode register
 2016-01-11 21:35:57 -05:00
Andreas Olofsson
34d1049bab Adding list of resources 2016-01-11 20:51:27 -05:00
Andreas Olofsson
bed1ba5556 Fixing write to TX register bug 
- The write transaction was incorrectly piped through to axi slave
 2016-01-11 20:50:40 -05:00
Andreas Olofsson
99e58fb56e Adding reset to pipeline 
- More conservative (only 2 more flops)
 2016-01-11 20:49:31 -05:00
Andreas Olofsson
fa42bc6e2e Reset simulation issue 
- Feels like I have seen this before, but still makes me nervous. The async negedge of reset was never being triggered in simulation by iverilog, probably because the simulation initialized it to 0, so there was no negedge. In logic, this is an async level signal....
 2016-01-11 20:47:06 -05:00
Andreas Olofsson
a68bba1572 Cleaning up register interface 
- Removed the cfgif block, too confusing. There is a good lesson here. Probably the n'th time I that I have been overzealous about reuse. When you end up adding a parameter to a block that duplicates the logic 2X it's always better to create two separate blocks...
- Changed the register access interface to packet format
- Change the priority on the etx_arbiter to pick read responses first
- Removed redundant signals
- Took away the read resonse bypass on remap in tx for now..
- Removed defparams (convention)
- Unified wait signal on tx
- Fixed cfg wait
-
 2016-01-11 17:35:53 -05:00
Andreas Olofsson
307794711d Error message in one hot mux 2016-01-11 17:35:15 -05:00
Andreas Olofsson
d1062fbff8 Changing dp memory interface in calling module 2016-01-11 17:34:35 -05:00
Andreas Olofsson
d4c5118a72 Making single/dual port memory interfaces constistant 2016-01-11 15:06:22 -05:00
Andreas Olofsson
4a454d71bd Making AW main parameter 2016-01-11 15:05:21 -05:00
Andreas Olofsson
152ee815e3 Making default 32bit for ease of use 2016-01-11 15:04:20 -05:00
Andreas Olofsson
1d540e7b49 Adding comments to table 2016-01-10 17:06:08 -05:00
Andreas Olofsson
eb8a29285d Cleanup 2016-01-10 16:45:16 -05:00
Andreas Olofsson
2279137d39 Merge branch 'master' of https://github.com/parallella/oh 
Conflicts:
	emailbox/hdl/emailbox.v
 2016-01-10 16:37:20 -05:00
Andreas Olofsson
32522280e6 Cleanup 2016-01-10 15:58:28 -05:00
Andreas Olofsson
5f16bd672e Changing test extension to "*emf" 
- The last field is a delay argument for stimulus
 2016-01-10 15:55:58 -05:00
Andreas Olofsson
becff479ca Refactoring (methodology) 2016-01-10 15:19:27 -05:00
Andreas Olofsson
c1da2531e6 Formatting 2016-01-10 15:18:40 -05:00
Andreas Olofsson
2feced7041 Methodology clarification 2016-01-10 15:16:24 -05:00
Andreas Olofsson
3168228174 Adding functionality for various modules 
(Work in progress, not tested)
 2016-01-10 13:33:31 -05:00
Andreas Olofsson
d5d315b5b9 Adding missing parameter 2016-01-10 11:59:14 -05:00
Andreas Olofsson
55eeafe0db Compile cleanup 2016-01-10 11:58:54 -05:00