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mirror of https://github.com/aolofsson/oh.git synced 2025-01-17 20:02:53 +08:00

494 Commits

Author SHA1 Message Date
Andreas Olofsson
ca5db9fa4d Interface cleanup
- fifo interface changes
- maxi/saxi name changes
- general code cleanup
- register remapping for mailbox
2016-01-19 13:33:08 -05:00
Andreas Olofsson
1a7a76e190 Removing filter logic for ID match (bug fix)
- This was moved to arbiter block
2016-01-19 13:32:26 -05:00
Andreas Olofsson
e8794b780c Simplifying axi_elink testbench
- Too much junk in there, couldn't understand my own logic 4 weeks later...
- emesh_if is a disaster, I have yet to find a way to write code that lets me remember the pass through bidirectoral logic for more than 1 day. Removed the interface and replaced it with 3 lines of code.
2016-01-19 13:30:09 -05:00
Andreas Olofsson
ce7c89ce1e Fixing read response logic
- Should only pass back read response EGROUP_RR
- Otherwise there would be a match on writing to MAILBOX
2016-01-19 13:27:22 -05:00
Andreas Olofsson
240e5b433c Moving mailbox registers to new addres
-Mailbox is a pretty useful little block, registers don't belong in the RX space
-Moved registers to the "MESH" group block at bits [10:8].
-Feel good about this, should not change...
-Has been tested  to work with test/test_regs.emf
-For new register address, see README.md

cc @olajep @peteasa
2016-01-16 14:44:35 -05:00
Andreas Olofsson
0bcab09269 Cleaning up unused constants 2016-01-16 14:42:57 -05:00
Andreas Olofsson
cd17b8130d Adding support for 64core board 2016-01-13 15:32:46 -05:00
Andreas Olofsson
c6bf2e2bb9 Removing "bid" parameter from emmu
-Access signal decoded from outside
2016-01-13 15:31:38 -05:00
Andreas Olofsson
6f6413eddc Updated regs test 2016-01-13 15:30:37 -05:00
Andreas Olofsson
b56da83aeb Clarifying R/W permissions on some registers 2016-01-12 09:02:37 -05:00
Andreas Olofsson
57c44bafb1 Fixing MMU write access
- MMU was being written when it shouldn't
2016-01-12 09:02:00 -05:00
Andreas Olofsson
804edcbc67 Adding reset signal to burst 2016-01-12 09:00:36 -05:00
Andreas Olofsson
f283b87e9d Adding elink_monitor
- Burst not supported
2016-01-12 08:38:45 -05:00
Andreas Olofsson
2bbe1e11b1 Change to TXCFG register!
- Made room for extra bit in ctrlmode register
2016-01-11 21:35:57 -05:00
Andreas Olofsson
bed1ba5556 Fixing write to TX register bug
- The write transaction was incorrectly piped through to axi slave
2016-01-11 20:50:40 -05:00
Andreas Olofsson
99e58fb56e Adding reset to pipeline
- More conservative (only 2 more flops)
2016-01-11 20:49:31 -05:00
Andreas Olofsson
a68bba1572 Cleaning up register interface
- Removed the cfgif block, too confusing. There is a good lesson here. Probably the n'th time I that I have been overzealous about reuse. When you end up adding a parameter to a block that duplicates the logic 2X it's always better to create two separate blocks...
- Changed the register access interface to packet format
- Change the priority on the etx_arbiter to pick read responses first
- Removed redundant signals
- Took away the read resonse bypass on remap in tx for now..
- Removed defparams (convention)
- Unified wait signal on tx
- Fixed cfg wait
-
2016-01-11 17:35:53 -05:00
Andreas Olofsson
2279137d39 Merge branch 'master' of https://github.com/parallella/oh
Conflicts:
	emailbox/hdl/emailbox.v
2016-01-10 16:37:20 -05:00
Andreas Olofsson
32522280e6 Cleanup 2016-01-10 15:58:28 -05:00
Andreas Olofsson
5f16bd672e Changing test extension to "*emf"
- The last field is a delay argument for stimulus
2016-01-10 15:55:58 -05:00
Andreas Olofsson
becff479ca Refactoring (methodology) 2016-01-10 15:19:27 -05:00
Andreas Olofsson
b130ac8fea Making AW in emesh2packet / packet2emesh explicit parameter 2016-01-10 11:51:49 -05:00
Peter Saunderson
a442dd4171 Updated mailbox test software and added trial kernel files
Signed-off-by: Peter Saunderson <peteasa@gmail.com>
2015-12-20 19:59:35 +00:00
Andreas Olofsson
d558bd5f99 Packet converter interface changes
-packet2emesh and emesh2packet had interface name changes
2015-12-17 12:51:22 -05:00
Andreas Olofsson
d5edb1ca88 Fixing priority on etx_arbiter
- don't do a combinatorial loopback on wait in a primitive cell, just bad practice...
- changed priority to give readback priority over read, safer?
2015-12-04 03:36:42 -05:00
Andreas Olofsson
de012ec9c8 Changes to oh common modules
- Converting some modules to be more ASIC friendly
2015-12-04 03:12:07 -05:00
Andreas Olofsson
7b8460b145 Fixing up issues with database reorg
- Not sure where the prog_full issue popped up from. (sign of disorganized databsae)
-
2015-11-30 15:07:28 -05:00
Andreas Olofsson
19fa611bb9 Massive reorganization to impove reuse
- adding more chip code
- pushing memory stuff into common
- making common "oh_" naming class
-
2015-11-30 13:45:49 -05:00
Andreas Olofsson
ddfeebd33f Cleaning up read response logic
- Bypass path was ugly! Always try to go through the same logic path as much as possible.
- Note: when MMU is enabled, you need to put in entry for read return (ie 810)
2015-11-29 19:07:28 -05:00
Andreas Olofsson
082593b2e9 Adding tests for mmu and remapping logic 2015-11-29 19:06:31 -05:00
Andreas Olofsson
7e49b29a79 Moving tests for idelay, mailbox, timeout from epiphany-examples
-Idea is to create complete packages
-All hardware modules should be complete, separation of tasks/sources can drive 10x in dev cost.
2015-11-29 12:44:22 -05:00
Andreas Olofsson
3ce9b41726 Working mailbox!
- Gating mailbox_not empty with irq_en. bit [28] of RXCFG
- Changing elink output interrupt to "or" of not_empty and full
- Adding mailbox status register (mostly for debug)
- Moving register addresses to make space for mailbox status register
- Fixing wrappers for DV
- Updating README docs with new register map
- Removing mailbox from RX status reg. Doesn't belong there, should be coupled with mailbox for modularity.
2015-11-29 12:20:17 -05:00
Andreas Olofsson
711088a9e7 Fixed mailbox bug on remap
- Bypassing remap on write to RX registers
- Otherwise the write to mailbox gets dropped since 810 gets remapped to 310
2015-11-29 12:10:53 -05:00
Andreas Olofsson
13005e6cbf Updated mailbox test
- Added mailbox status address
- Moved mailbox registers
2015-11-29 12:09:47 -05:00
Andreas Olofsson
2ca649394b Adding timeout response code 2015-11-29 10:27:43 -05:00
Andreas Olofsson
ad568ad0a0 Implementing simple 64K cycle timeout for slave interface 2015-11-28 22:31:39 -05:00
Andreas Olofsson
099dbececa Adding test for mailbox readback 2015-11-28 21:42:05 -05:00
Andreas Olofsson
c294ba7775 Fixing readback from mailbox 2015-11-28 21:41:18 -05:00
Andreas Olofsson
0fc4b6188a Test cleanup
- added lint script using verilator
- adding verilator filter commands for fifo behavioral
- Longer pushbacks in ememory
2015-11-28 20:15:06 -05:00
Andreas Olofsson
1890657d6d Solved read response bug. MATMUL WORKS!!!!
- Turns out I was debugging ghosts for ~1 day today. Everything was working in simulation but nothing works in the FPGA. Since I was only changing small logic stuff, I didn't bother checking the warning messages in Viviado. Turns out for some reason it was throwing away some logic and disconnecting all the important rr signals
- This is where I was making changes, but I still can't figure out what exactly was happening...doesn't make sense. Either there is a bug in icarus or in vivado, this shouldn't happen!
2015-11-25 23:50:29 -05:00
Andreas Olofsson
08f5d28ed4 Test cleanup 2015-11-25 23:49:56 -05:00
Andreas Olofsson
8856f7c763 DV cleanup 2015-11-25 22:00:07 -05:00
Andreas Olofsson
045652cc10 Adding TXPACKET register to doc 2015-11-25 21:59:43 -05:00
Andreas Olofsson
d66317abbc Fixing bug for readback??
- There was definitely a bug there, that has been fixed
- But now the interface seems completely broken...
- Passes in simulation and "should work"...
2015-11-25 21:57:25 -05:00
Andreas Olofsson
379099da9c Filtering register write transactions
-They were going out on the elink (not safe)
2015-11-25 21:56:56 -05:00
Andreas Olofsson
33d5fb72e1 Filtering out short wait-low pulses from legacy elink
-Feels safer, should not be any short wait glitches
2015-11-25 21:55:37 -05:00
Andreas Olofsson
40c0c95791 Fixing clock transfer speedpath
- Better to do shift register than a wide or pulse
2015-11-25 21:54:02 -05:00
Andreas Olofsson
e5163d4d82 Adding debug logic to elink
- packet capture register
- transaction counter logic
2015-11-25 21:53:33 -05:00
Andreas Olofsson
eb0ad74973 Adding testing/motnirot logic to link
- RX/TX satus registers with sticky bits
- monitor register for checking number of valid transactions
2015-11-25 12:50:02 -05:00
Andreas Olofsson
4228fccd56 Adding debug features to elink
- Adding RX/TX sticky monitors bits in STATUS register
- Adding burst enable bit for debugging. Turned off by default.
2015-11-25 10:18:02 -05:00