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Commit Graph

Author	SHA1	Message	Date
Andreas Olofsson	381ba09617	Making CFG_ASIC a primary variable -Need to separate between open FPGA design and closed ASIC design. -NDAs means it's imposssible for us to disclose even the interfaces of the cells inside without taking the risk of violating the terms of the NDA. -For this reason, we come up with generic and clean asic library interfaces that need to be implemented in each library/technology	2016-06-19 17:05:50 -04:00
Andreas Olofsson	c3b83621e0	Reorg cleanup	2016-03-22 08:27:59 -04:00
Andreas Olofsson	7094173ae9	Reorg! Why? - The top level directory was not scaling, too imposing - Friendlier to download a repo and see a finite number of top level dirs - We are just getting started...	2016-03-22 08:13:40 -04:00

Author

SHA1

Message

Date

Andreas Olofsson

381ba09617

Making CFG_ASIC a primary variable

-Need to separate between open FPGA design and closed ASIC design.
-NDAs means it's imposssible for us to disclose even the interfaces of the cells inside without taking the risk of violating the terms of the NDA.
-For this reason, we come up with generic and clean asic library interfaces that need to be implemented in each library/technology

2016-06-19 17:05:50 -04:00

Andreas Olofsson

c3b83621e0

Reorg cleanup

2016-03-22 08:27:59 -04:00

Andreas Olofsson

7094173ae9

Reorg! Why?

- The top level directory was not scaling, too imposing
- Friendlier to download a repo and see a finite number of top level dirs
- We are just getting started...

2016-03-22 08:13:40 -04:00

3 Commits