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Commit Graph

Author	SHA1	Message	Date
Andreas Olofsson	d26d3efbc1	Fixing fifo status for mtx (signals were unconnected)	2016-03-21 14:29:59 -04:00
Andreas Olofsson	18084bf63f	MIO cleanup -adding target parameter to fifo -fixing rx protocol bugs -adding defaults to register file, usually these should be set to zero and -don't clock gate the DDR TX, just causes output to toggle like clock, BAD! -fixed status register sticky bug -adding autoincrement feature in amode -fixing dut file for new "mio" subsystem -emesh packet now goes through in loopback!!!	2016-03-21 11:27:35 -04:00
Andreas Olofsson	fec6a98d90	Refactoring mio - changing datapath name to mio_dp (new methodology) - top level should be complete block (with control + clock) for ease uf use - clock renaming	2016-03-21 06:15:50 -04:00

Author

SHA1

Message

Date

Andreas Olofsson

d26d3efbc1

Fixing fifo status for mtx

(signals were unconnected)

2016-03-21 14:29:59 -04:00

Andreas Olofsson

18084bf63f

MIO cleanup

-adding target parameter to fifo
-fixing rx protocol bugs
-adding defaults to register file, usually these should be set to zero and
-don't clock gate the DDR TX, just causes output to toggle like clock, BAD!
-fixed status register sticky bug
-adding autoincrement feature in amode
-fixing dut file for new "mio" subsystem
-**emesh packet now goes through in loopback!!!**

2016-03-21 11:27:35 -04:00

Andreas Olofsson

fec6a98d90

Refactoring mio

- changing datapath name to mio_dp (new methodology)
- top level should be complete block (with control + clock) for ease uf use
- clock renaming

2016-03-21 06:15:50 -04:00

3 Commits