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1,438 Commits 7 Branches 1 Tag
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139 Commits

Author SHA1 Message Date
Andreas.Olofsson
bc76414aa5 Fixing crucial reset bug in dsync 2020-08-17 23:14:21 -04:00
Andreas.Olofsson
6d1735d3b9 Fixing a bunch of synthesis issues 
-Better to fix to avoid issues across different synthesis platform
(even if standard would allow if for verilog2005)
 2020-08-17 16:11:42 -04:00
Andreas.Olofsson
76e6cd3c15 Fixing concatenation bug 
-Don't use concatenation for generators!
-Will failt for DW=1
 2020-08-14 10:38:03 -04:00
Andreas.Olofsson
5c0df270c5 Belated fix of register file 
-Simulated correctly, but did not synthesize in DC
 2020-08-08 22:23:45 -04:00
Andreas.Olofsson
0d61520268 Fixed issue with DC verilog parser 
-Apparentely "|=" is not allowed??
 2020-08-08 22:22:52 -04:00
Andreas.Olofsson
7abc91751a Fixing basic register file bug 
-Working in simulation but was not synthesizable by DC
 2020-07-27 19:56:11 -04:00
Andreas.Olofsson
9147a49103 Fixing basic carry bug in the csa4:2 
(carry was wrong)
 2020-07-20 22:51:58 -04:00
Andreas.Olofsson
ae6cdc912e Mapping cs42 to csa32 
-Better synthesis results
 2020-07-20 14:50:09 -04:00
Andreas.Olofsson
126f859908 Adding clock enable for register 
-Removing the ASIC CFG as well...have to rethink that concept, not really working
 2020-07-14 13:48:42 -04:00
Andreas.Olofsson
d7639390f4 Typo fix 2020-04-23 22:44:47 -04:00
Andreas.Olofsson
58eedb914d Cleanup 2020-04-22 23:17:25 -04:00
Andreas.Olofsson
a7870ac9de Cleaned up counter 
-Not functional
 2020-04-22 23:15:12 -04:00
Andreas.Olofsson
d9897a1bec Multi-type multiplier working 
-only reference model implemented
-Next, implement complete algorithm and output partial products
 2020-04-09 21:42:28 -04:00
Andreas.Olofsson
d6b6e1bd76 Adding basic multiplier stub 2020-04-09 14:58:29 -04:00
Andreas.Olofsson
97bc8d08af Name change one last time... 2020-04-07 10:25:54 -04:00
Andreas.Olofsson
8b39f7e444 Fixing register file 
-Changing DW to RW (RW not always equal to DW..)
-Blocking rd_data on valid
-Fixing elemetary bugs based on indices
-Simplifying index code
-Add configurable pipeline stage?
 2020-04-07 10:23:35 -04:00
Andreas.Olofsson
68829c93d0 Adding dumpvar to interface 2020-04-02 22:14:07 -04:00
Andreas.Olofsson
32b103d290 Adding parametrized register file 2020-04-02 22:13:07 -04:00
Andreas.Olofsson
18bb820f56 Merge branch 'master' of github.com:aolofsson/private-oh 2020-03-28 15:40:11 -04:00
Andreas.Olofsson
c271360709 Changing order of RAM array 2020-03-28 15:38:29 -04:00
Andreas.Olofsson
281a19d7bf Adding debug features to fifo_sync 
-Ability to dump array
-Error on attempt to write to fifo while full
 2020-03-26 12:24:45 -04:00
Andreas.Olofsson
5269354461 Adding ability to dump array for iverilog 
-Important for FIFO debugging
 2020-03-26 12:24:01 -04:00
Andreas.Olofsson
7b33ff0405 Fixing yet another fifo bug... 2020-03-20 20:39:15 -04:00
Andreas.Olofsson
3c8be0c083 Fixing brain-dead bug! 
-I guess nobody has been using this fifo, because it was hoplessly broken. Fucking sad.
 2020-03-13 12:24:35 -04:00
Andreas.Olofsson
bee941aa61 Adding reset wakup event to standby module 
-Create an event at rising edge of reset
-Turn on the clock for long enough to allow for reset signal to get turned on
-Note the race here! This is why the rest and standby needs to be combined into one block.
 2020-03-13 11:05:49 -04:00
Andreas.Olofsson
412fb61519 Changing delay function to take a clock 
-The combinatorial delay elemement doesn't belong in this library, too specific!
 2020-03-13 11:04:08 -04:00
Andreas.Olofsson
04675f49a7 Adding synchronous clear signal to fifo 
-It's not uncommon to want to clear/invalidate all entries int he FIFO
-Still need async reset for power-on in absence of clocks
 2020-03-13 11:02:49 -04:00
Andreas.Olofsson
2b2c719765 Fixing another bug (PS vs N) 2020-03-04 21:12:24 -05:00
Andreas.Olofsson
4f0f81997e Fix datagate bug! 
-Was not turned on at all! Alwats on
 2020-03-04 18:36:38 -05:00
Andreas.Olofsson
9e9d323025 Changing the CFG_ASIC approach 
-Should be ifdef, since this is a global. You will never be doing and not an asic at the same time!
 2020-02-04 23:04:52 -05:00
Andreas.Olofsson
21349445ef Change macro name to reduce confusion 2020-02-04 22:43:18 -05:00
Andreas.Olofsson
b057d47d57 Duh, fixing CFG_ASIC issue! 
-It's a global, use ifdef to avoid compilation issues
-No need for generate
 2020-02-02 23:12:19 -05:00
Andreas.Olofsson
d6f5de24d7 Changing hierarchy to promote blocks 2020-01-28 18:12:57 -05:00
Andreas Olofsson
7094173ae9 Reorg! Why? 
- The top level directory was not scaling, too imposing
- Friendlier to download a repo and see a finite number of top level dirs
- We are just getting started...
 2016-03-22 08:13:40 -04:00
Andreas Olofsson
3ae9c26d38 Changing shift/load order 
- Load should always have higher priority, but load is blocked if there is a pending shift anyway...
 2016-03-21 20:50:41 -04:00
Andreas Olofsson
b89f451c2f Fixing basic par2ser stall bug 
- don't start new transfer until current transfer is done
 2016-03-21 14:32:15 -04:00
Andreas Olofsson
93154c38f8 Adding special div2 logic for clock divider 
- Using negedge of clock for phase shifting 2nd clock by 90 degrees. Used by elink and mio
 2016-03-21 11:19:25 -04:00
Andreas Olofsson
3fa5fce86f Cleaning up fifos 
- Making default parameter generic (will need to fix elink next..)
- Brining out fifo status for cdc module, goes to status registers (very useful for debugging)
 2016-03-21 11:18:07 -04:00
Andreas Olofsson
b61d55533e Fixing par2ser bugs 
-access out signal was broken (may need to fix again for spi)
-lsbfirst mode was broken
-made datasize 8 bits at interface
 2016-03-21 11:16:42 -04:00
Andreas Olofsson
e5a8227509 Adding features to clock divider 
-splitting out period from phase
-adding a second phase shifted clock (running off one counter)
-adding orthogonal control of rising and falling edge
 2016-03-20 18:17:26 -04:00
Andreas Olofsson
015b969ac2 Making default parameter N=1 for muxes 
- Less reconfiguring of parameters at instantiation time
 2016-03-17 23:41:56 -04:00
Andreas Olofsson
3ca89dca2b Fixed serializer bug 
- ..hopefully last one
- incorrect stall signal made transactions get lost
 2016-03-10 17:33:02 -05:00
Andreas Olofsson
ed8d29ee2c Fixing serializer bug 
- SPI now working...
 2016-03-10 17:03:38 -05:00
Andreas Olofsson
da6856befa Adding reset signal to pulse interfaces 
- Needed for some logic with feedback, otherwise you get "x" loop
- Those who don't need it should be able to connect nrest to 1'b1
 2016-03-10 17:02:03 -05:00
Andreas Olofsson
383dd50b99 Fixed lethal off by one fifo full bug! 2016-03-10 14:58:29 -05:00
Andreas Olofsson
a5b4768b3b Vectorizing edge2pulse module 2016-03-10 11:07:14 -05:00
Andreas Olofsson
e900ecca2a Simplifying clockdiv 
-tested in spi block
-more generic, simpler
 2016-03-10 11:06:28 -05:00
Andreas Olofsson
d129b93040 Adding edge specific pulse generators 2016-03-10 11:05:36 -05:00
Andreas Olofsson
8c350eed91 Debugged most of SPI 
-Changed to FIFO on TX path (cleaner)
-No good solution on RX with CDC since clock can stop, so you can't use an async fifo.
-Slave needs cleanup, rethink...
-Using commong par2ser and ser2par blocks
 2016-03-09 22:46:24 -05:00
Andreas Olofsson
ef790c1a59 Expanding par2ser functionality 
-module now works for multi bit shifts
-has been used in spi master module
-versatile load and shift bits
 2016-03-09 21:11:17 -05:00