Andreas Olofsson
be42ea3b89
Register map change
...
-Changed register map
-Splitting into groups, more natural
2015-04-24 17:38:01 -04:00
Andreas Olofsson
79467583c9
Made reset async (there may not be a clock..)
2015-04-24 17:32:17 -04:00
Andreas Olofsson
ea7683693c
Adding RX/TX address remapping
...
The MMU is a monster and may be too much
Adding simple remapping modules
Covers todays feature and then some
1.) Static remapping
2.) Addresss compression
2015-04-24 17:29:05 -04:00
Andreas Olofsson
b25ad633f7
Readback cleanup
...
RX/TX interfaces should be mininmized and standalone
Adding mux to consolidate to one "dout"
2015-04-24 17:27:35 -04:00
Andreas Olofsson
3b637e55f0
MILESTONE: Design once again passes test
...
New features:
DMA
MAILBOX directly in RX path
TXMMU
2015-04-23 23:16:03 -04:00
Andreas Olofsson
0ed6afeac9
Added tag and group for read response
...
-Still not sure about this..
2015-04-23 23:14:39 -04:00
Andreas Olofsson
370034437f
Added proper 64bit write port to mailbox
2015-04-23 23:14:04 -04:00
Andreas Olofsson
46896c63ef
Bug fix, adding reset signal
...
This will blocking when there is no clock at startup.
2015-04-23 23:13:05 -04:00
Andreas Olofsson
24fc91072d
Adding IDs to keep access signals straight
2015-04-23 23:11:58 -04:00
Andreas Olofsson
5af7a745b1
Created separate IDs for RX and TX
...
-We want to make the two directions as separate as possible so no shared variables. Still need a tag for differentiating between write and read response. In addition we need a group to keep the rr separate from mailbox write.
git diffgit c
2015-04-23 23:10:27 -04:00
Andreas Olofsson
01fec0f72a
Fixed elink missind ID parameter
2015-04-23 20:07:52 -04:00
Andreas Olofsson
5c8fb41849
Fifo read bug
...
-fifo should be read when it's not empty and there is no wait pushback
2015-04-23 20:07:10 -04:00
Andreas Olofsson
c4c1edc10f
Adding reset to critical signals in pipe
2015-04-23 20:06:11 -04:00
Andreas Olofsson
21173fef95
Forgot "posedge reset"
2015-04-23 20:05:51 -04:00
Andreas Olofsson
7ab3b3a8f8
Fixed floating net bug
2015-04-23 20:05:00 -04:00
Andreas Olofsson
74fe62e94d
Broken testbench connections
2015-04-23 20:04:03 -04:00
Andreas Olofsson
0f0ff55928
Verilator based lint cleanup
2015-04-23 18:57:55 -04:00
Andreas Olofsson
5ac06cd772
Fixed stupid typos on full/empty
...
Surprised it wasn't caught during iverilog compile
2015-04-23 18:56:49 -04:00
Andreas Olofsson
155f6a9401
File cleanup
2015-04-23 18:10:07 -04:00
Andreas Olofsson
ec68dddd99
Packet interface changes
2015-04-23 18:09:16 -04:00
Andreas Olofsson
842dd60b3e
Adding DMA register to regmap
2015-04-23 18:08:52 -04:00
Andreas Olofsson
c76bce1ea3
Changing so basic elink unti is without AXI
2015-04-23 18:08:20 -04:00
Andreas Olofsson
fcf5bf010f
Splitting register file into separate pieces
2015-04-23 18:07:50 -04:00
Andreas Olofsson
ec0c9ce835
Changing to packet interface
2015-04-23 18:07:27 -04:00
Andreas Olofsson
ed0b8c2539
Major RX change:
...
-renamed interfaces to rxwr,rxrd,rxrr (much simpler to remember for me)
-packet interface change
-removed wait signals from dataout field
-added dma, emmu, mailbox, config register
-instantiating fifo_sync raw (without wrapper)
2015-04-23 18:04:39 -04:00
Andreas Olofsson
2707541eab
Adding DMA source and changing interface
...
-DMA added as a master driving out transactions
(this is going to be great!!)
-Changing to packet interface
2015-04-23 18:03:10 -04:00
Andreas Olofsson
842a6d894a
Fixing enable/reset:
...
-Removing enable from ISERDES, not healthy
-Moving all logic to protocol block. (this is an IO block)
-Removing tow redundant pipeline stages (check this??)
2015-04-23 18:01:19 -04:00
Andreas Olofsson
7418d45f5e
Cleanup
...
-Packet interface change
-Adding RX enable logic with synchronizer (better place than erx_io)
2015-04-23 17:59:36 -04:00
Andreas Olofsson
d9525b6ae4
Major upgrade
...
-Adding DMA, EMMU, CFG
-Removing redundant signals
-Changing to packet interface
2015-04-23 17:58:18 -04:00
Andreas Olofsson
9a614d1094
Packet interface change
2015-04-23 17:57:24 -04:00
Andreas Olofsson
44f162ec09
Packet interface change
...
-Changed packet interface
-Removed rd/wr from block, was pass through
2015-04-23 17:56:15 -04:00
Andreas Olofsson
31e721cea7
Interface change
...
Changed to packet interface
Changed name to "mailbox"
2015-04-23 17:54:59 -04:00
Andreas Olofsson
8266e6dd29
Changing to packet interface
2015-04-23 17:54:23 -04:00
Andreas Olofsson
34813035bc
Changing FIFO interface
...
More inline with standard Xilinx fifo
names, names, names..ugh
2015-04-23 17:53:22 -04:00
Andreas Olofsson
62c2c0e654
Adding comments
2015-04-23 17:52:46 -04:00
Andreas Olofsson
35d6c3934f
Comments
2015-04-23 17:52:06 -04:00
Andreas Olofsson
1e1644138e
Splitting register file (rx,tx,base)
...
The goal is to have 100% independence in RX and TX pipes
2015-04-23 17:50:45 -04:00
Andreas Olofsson
0d10fbd26f
Adding more docs
2015-04-23 17:50:16 -04:00
Andreas Olofsson
028fac446e
Adding an emesh DMA
2015-04-23 17:49:06 -04:00
Andreas Olofsson
8770696d87
Massive commit sequence coming...
2015-04-23 17:48:12 -04:00
Andreas Olofsson
2b22d1c4af
Adding emesh to packet converters
...
-getting tired of all the typing after all....
2015-04-22 16:43:52 -04:00
Andreas Olofsson
cc5f165454
Clarified lclk names
2015-04-22 15:03:24 -04:00
Andreas Olofsson
c225349639
Updated clocking diagram
2015-04-22 15:02:50 -04:00
Andreas Olofsson
703da8445b
deleted junk
2015-04-22 15:02:31 -04:00
Andreas Olofsson
bc71401888
Adding elink clocking diagram
2015-04-22 13:58:51 -04:00
Andreas Olofsson
797d836a02
Renaming constants file
2015-04-22 13:56:48 -04:00
Andreas Olofsson
617214cc90
Cleanup
2015-04-22 13:56:29 -04:00
Andreas Olofsson
77d41cfe4e
Adding PLL and MMCME2 primitives
2015-04-22 13:55:59 -04:00
Andreas Olofsson
1508afa2ea
Adding a "max" ps7 system for reference
...
Not convinced that it's good to do this in text...
(but it's always good to know what's underneath the hood)
Vivado IP generates wrappers after all
2015-04-22 13:54:52 -04:00
Andreas Olofsson
fce122565d
Adding README file for xilibs
2015-04-21 21:52:20 -04:00
