-renamed interfaces to rxwr,rxrd,rxrr (much simpler to remember for me)
-packet interface change
-removed wait signals from dataout field
-added dma, emmu, mailbox, config register
-instantiating fifo_sync raw (without wrapper)
-added register read/write properly
-removed redundant wrapper layers in maxi/saxi
-changed over to "emesh" interface from packet 103 bit data
-cleaned up maxi
-cleaned up saxi
-removed redundant signals in elink interface (user,lock,..)
-added wrapper to fifo (to carry emesh interface through)
Now comes the fun part of testing
Our "standard packet" order should be followed everywhere to ease verification and integration (standards are good fir reuse...):
[0]=access
[1]=write
[3:2]=datamode
[7:4]=ctrlmode
[39:8]=dstaddr
[71:40]=data
[103:72]=upper-data (or srcaddr)
