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1,448 Commits 7 Branches 1 Tag
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219 Commits

Author SHA1 Message Date
Andreas.Olofsson
c215b48a55 Redesining oh_iddr 
-adding separate clock enables
-adding internal clock enable for neg edg sample
-combining q1/q2 legacy interfae into a single output
 2020-09-23 16:48:10 -04:00
Andreas.Olofsson
fda0f35dd9 Name change to packets 
-Using valid signal instead of access, more standardized
 2020-09-23 16:47:13 -04:00
Andreas.Olofsson
f817bb57ec Removing redundant code in async fifo instance 2020-09-23 16:46:46 -04:00
Andreas.Olofsson
acd469e933 Removing extra pipeline dela in ODDR 
-Both din1 and din2 needs to be stable low by driver
-If the inputs are driven by a reg anyway like in the case of a FIFO output or memory, then we just saved a cycle of redundant latency
 2020-09-22 10:57:00 -04:00
Andreas.Olofsson
6be20de08b Day zer big???!!! 
-Can't believe this was missed!!!!!
-Clearly for a dual data rate circuit, a stable low signal should be selected with low clock, that's the definition!
 2020-09-22 10:31:38 -04:00
Andreas.Olofsson
30419a5239 Adding generic IO buffer 2020-09-21 13:54:06 -04:00
Andreas.Olofsson
89f995c20c Fixed nasty testbench problem that snuck in 
-The pass fail indicator is always tricky to get right
-In this case diff/done went high on the same cycle so everything was passing..
-Added check for same cyle completion/fail
-Also, changed the top level anme to "testbench", seems more popular
 2020-08-19 19:34:03 -04:00
Andreas.Olofsson
028dcd886d Bug fix, adding missig reset signal 2020-08-17 23:16:06 -04:00
Andreas.Olofsson
ec26479567 Adding missing ports to dual port memory 
-Seems excessive?
 2020-08-17 23:15:00 -04:00
Andreas.Olofsson
bc76414aa5 Fixing crucial reset bug in dsync 2020-08-17 23:14:21 -04:00
Andreas.Olofsson
6d1735d3b9 Fixing a bunch of synthesis issues 
-Better to fix to avoid issues across different synthesis platform
(even if standard would allow if for verilog2005)
 2020-08-17 16:11:42 -04:00
Andreas.Olofsson
6ae99dbba4 Fixing priority problem withy pass/done 
-When diff gets stuck high, test would timeout
 2020-08-17 16:10:03 -04:00
Andreas.Olofsson
58ee16092e Changing simchecker to hex. 
-Not practical for broad use with binary
 2020-08-17 16:09:32 -04:00
Andreas.Olofsson
76e6cd3c15 Fixing concatenation bug 
-Don't use concatenation for generators!
-Will failt for DW=1
 2020-08-14 10:38:03 -04:00
Andreas.Olofsson
5c0df270c5 Belated fix of register file 
-Simulated correctly, but did not synthesize in DC
 2020-08-08 22:23:45 -04:00
Andreas.Olofsson
0d61520268 Fixed issue with DC verilog parser 
-Apparentely "|=" is not allowed??
 2020-08-08 22:22:52 -04:00
Andreas.Olofsson
d7769070fc Adding diff and sticky flag to ease debugging 
-One flag for end of test pass fail
-Seond flag for gtkwave to see where all the fails happen
 2020-07-27 19:56:57 -04:00
Andreas.Olofsson
7abc91751a Fixing basic register file bug 
-Working in simulation but was not synthesizable by DC
 2020-07-27 19:56:11 -04:00
Andreas.Olofsson
9147a49103 Fixing basic carry bug in the csa4:2 
(carry was wrong)
 2020-07-20 22:51:58 -04:00
Andreas.Olofsson
ae6cdc912e Mapping cs42 to csa32 
-Better synthesis results
 2020-07-20 14:50:09 -04:00
Andreas.Olofsson
9ac530e526 Adding indication that test started for regression clarity 2020-07-19 10:12:07 -04:00
Andreas.Olofsson
84e8449cb5 Moving sampling to negedge for clarity 2020-07-14 13:50:24 -04:00
Andreas.Olofsson
126f859908 Adding clock enable for register 
-Removing the ASIC CFG as well...have to rethink that concept, not really working
 2020-07-14 13:48:42 -04:00
Andreas.Olofsson
d7639390f4 Typo fix 2020-04-23 22:44:47 -04:00
Andreas.Olofsson
58eedb914d Cleanup 2020-04-22 23:17:25 -04:00
Andreas.Olofsson
7c0e1bc01f Adding fail criteria to common simulation control infrastucture 
-Preparing for CI and unit tests for all modules
 2020-04-22 23:16:43 -04:00
Andreas.Olofsson
2c106bed5e Moving checker to positive edge 
-This should be synthesizable into FPGAs!
 2020-04-22 23:15:41 -04:00
Andreas.Olofsson
a7870ac9de Cleaned up counter 
-Not functional
 2020-04-22 23:15:12 -04:00
Andreas.Olofsson
d8d2d0c20e Changing dv_checker to oh_simchecker 
-library consistency
 2020-04-22 22:40:43 -04:00
Andreas.Olofsson
cf47e56436 Changing dv_* to oh_* to be consistent 2020-04-22 21:52:37 -04:00
Andreas.Olofsson
d9897a1bec Multi-type multiplier working 
-only reference model implemented
-Next, implement complete algorithm and output partial products
 2020-04-09 21:42:28 -04:00
Andreas.Olofsson
d6b6e1bd76 Adding basic multiplier stub 2020-04-09 14:58:29 -04:00
Andreas.Olofsson
97bc8d08af Name change one last time... 2020-04-07 10:25:54 -04:00
Andreas.Olofsson
8b39f7e444 Fixing register file 
-Changing DW to RW (RW not always equal to DW..)
-Blocking rd_data on valid
-Fixing elemetary bugs based on indices
-Simplifying index code
-Add configurable pipeline stage?
 2020-04-07 10:23:35 -04:00
Andreas.Olofsson
68829c93d0 Adding dumpvar to interface 2020-04-02 22:14:07 -04:00
Andreas.Olofsson
32b103d290 Adding parametrized register file 2020-04-02 22:13:07 -04:00
Andreas.Olofsson
18bb820f56 Merge branch 'master' of github.com:aolofsson/private-oh 2020-03-28 15:40:11 -04:00
Andreas.Olofsson
c271360709 Changing order of RAM array 2020-03-28 15:38:29 -04:00
Andreas.Olofsson
281a19d7bf Adding debug features to fifo_sync 
-Ability to dump array
-Error on attempt to write to fifo while full
 2020-03-26 12:24:45 -04:00
Andreas.Olofsson
5269354461 Adding ability to dump array for iverilog 
-Important for FIFO debugging
 2020-03-26 12:24:01 -04:00
Andreas.Olofsson
064ec792d3 Adding testname to simplfy grepping of regression suite results 2020-03-26 12:22:56 -04:00
Andreas.Olofsson
7b33ff0405 Fixing yet another fifo bug... 2020-03-20 20:39:15 -04:00
Andreas.Olofsson
3c8be0c083 Fixing brain-dead bug! 
-I guess nobody has been using this fifo, because it was hoplessly broken. Fucking sad.
 2020-03-13 12:24:35 -04:00
Andreas.Olofsson
bee941aa61 Adding reset wakup event to standby module 
-Create an event at rising edge of reset
-Turn on the clock for long enough to allow for reset signal to get turned on
-Note the race here! This is why the rest and standby needs to be combined into one block.
 2020-03-13 11:05:49 -04:00
Andreas.Olofsson
412fb61519 Changing delay function to take a clock 
-The combinatorial delay elemement doesn't belong in this library, too specific!
 2020-03-13 11:04:08 -04:00
Andreas.Olofsson
04675f49a7 Adding synchronous clear signal to fifo 
-It's not uncommon to want to clear/invalidate all entries int he FIFO
-Still need async reset for power-on in absence of clocks
 2020-03-13 11:02:49 -04:00
Andreas.Olofsson
2b2c719765 Fixing another bug (PS vs N) 2020-03-04 21:12:24 -05:00
Andreas.Olofsson
4f0f81997e Fix datagate bug! 
-Was not turned on at all! Alwats on
 2020-03-04 18:36:38 -05:00
Andreas.Olofsson
069681ca6a Typo fix in dv_ctrl 2020-02-17 07:43:41 -05:00
Andreas.Olofsson
a09374d74b Adding FAIL timeout condition in test 2020-02-15 21:58:17 -05:00