-Apparantly old FIFO was not pipelined (IE data comes back same cycle).
-Not knowing the Xilinx logic, I made it a regular one cycle pipeline
memory based FIFO
-Adding enable signal to clock out. Definitely right decision to keep
separate bit from the divider field.
-Fixed settings for to fit new register field
-XILINX version is still broken!!
-Moved "groups" to E,D,C
-Changed names to EL* (shorter is better, clear enough)
-Moved order to fit logical operation during init
-Moved embox registers to MMR group
DONE!
-This is as far as I go with fufu testing (random next)
-Add basic test for cleaning up reads/writes
-104 bit packet format for driving transactions, very useful
First time ever using spell cheker in EMACS. Hard to believe...but it's true!
I am sure this speaks volume for how little I have commented my code over the years!
old implementation felt too "cutsy"
this makes for a cleaner usage model (simple shift with param)
also splitting out enable but, not making the CTIMER mistake again
-adding reset signals to synchronizer to solve startup issues
-setting config in test bench for speedup, default reg config now correct
-fix (my) stupid bug in etx_arbiter
-adding reset to fifo (todo: review this!)
-reviewing "all red" from waveforms is a must. Red (x) on data is ok, but leaving them on control signals is asking for trouble. Better safe than sorry when it comes to reset.
-changed ecfg clock default values, elink default is now the PLL clock/128 coming out of reset
-should work in any implementation?
-still have to implement the Xilinx specific stuff
-pll bypass for clocks (customer request)
-adding dividers on all clocks (tx/cclk)
-adding reset block (clearer)
-using commong clock_divider block
-need to clean up divider block later today, slightly broken:-)
-First bug was a typo. Cursing AXI for making every signal look exactly the same at first glance. Not good use practice
-Second bug was sloppy. (removed pipeline stage on write data by mistake)
