9 Commits

Author	SHA1	Message	Date
Andreas Olofsson	d81bb66d73	Writing while full is aserted	2015-08-14 17:15:38 -04:00
Andreas Olofsson	c627827a6b	Fifo cleanup ... -Adding model (one source..) -generate for 104x32 for xilinx -making prog_full the default full indicator -bringing out almost_full for future use -fixing interface change in all modules	2015-07-02 16:59:38 -04:00
Andreas Olofsson	1eb2bcea89	Removing custom xilinx primitives ... -Using the memory_sp macro instead... -Cleaner design -axi_elink now works!	2015-05-21 22:54:29 -04:00
Andreas Olofsson	02cc0f2b4f	Adding reset to both sides of fifo	2015-05-14 22:47:25 -04:00
Andreas Olofsson	b2b7f96e86	Making FIFO/memories easier to use ... -WIDTH/DEPTH parameters -Removing references to "clean" in ifdefs	2015-05-07 23:50:34 -04:00
Andreas Olofsson	ec3dbc910a	Using async reste on fifo output access signal ... -For cases where there is no clock at output	2015-05-04 17:07:55 -04:00
Andreas Olofsson	75f653ffd6	Naming cleanup	2015-05-04 10:37:08 -04:00
Andreas Olofsson	19e22c38d7	Adding proper wait to fifo_cdc ... If there is a waitm, we should 1.) Not increment the read pointer 2.) Hold the packet steady until wait signal goes away 3.) Hold access high, keep request intact	2015-05-03 23:17:23 -04:00
Andreas Olofsson	a58c2d5279	Adding clock domain crossing module for emesh ... -Generic, built for reuse	2015-05-01 17:13:44 -04:00