Andreas Olofsson
c627827a6b
Fifo cleanup
...
-Adding model (one source..)
-generate for 104x32 for xilinx
-making prog_full the default full indicator
-bringing out almost_full for future use
-fixing interface change in all modules
2015-07-02 16:59:38 -04:00
Andreas Olofsson
5ac06cd772
Fixed stupid typos on full/empty
...
Surprised it wasn't caught during iverilog compile
2015-04-23 18:56:49 -04:00
Andreas Olofsson
c41a0a8640
Cleaning up licenses for consistency
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-All files still GPLv3
-Placed at the bottom of the file (I am tired of looking at them!)
2015-04-17 22:21:08 -04:00
Andreas Olofsson
7bc3b662ab
Added profull HACK to async_fifo
...
-this module needs rework
-needs to have same capabilities as standard FPGA async fifos
-remove this later
2015-04-17 15:49:58 -04:00
Andreas Olofsson
bee90fcacc
Support files for fifo
2015-04-14 23:56:59 -04:00
