3 Commits

Author	SHA1	Message	Date
Andreas Olofsson	d2cb9aa224	Refactoring and fixing bugs... ... -back and forth with emmu, memory is now inside (for good) -renamed clocks in etx to clarify -updated logic in protocol and disty -updated clock module ...one more review pass and we are ready for testing...	2015-03-25 19:25:12 -04:00
Andreas Olofsson	b0b9315bf1	Massive checkin... ... -this may break already broken projects -creates a Verilog top level (instead of using Vivado block level design) -integrates mmy and mailbox (not completely integrated) -compiles... -pours in all of the code from the archive (some new logic created)	2015-03-24 20:44:03 -04:00
aolofsson	4f51cc342d	Adding new verilog modules for receiver and transmitter ... -moving away from Vivado block editor -creating a "clean" split between RX and TX	2014-12-14 17:18:53 -05:00