-back and forth with emmu, memory is now inside (for good)
-renamed clocks in etx to clarify
-updated logic in protocol and disty
-updated clock module
...one more review pass and we are ready for testing...
-this may break already broken projects
-creates a Verilog top level (instead of using Vivado block level design)
-integrates mmy and mailbox (not completely integrated)
-compiles...
-pours in all of the code from the archive
(some new logic created)
