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Author SHA1 Message Date
Andreas Olofsson
c9f64a2fb2 Fixing dv to check axi_elink 
-Need to split these, getting too cumbersome
 2015-05-21 22:56:23 -04:00
Andreas Olofsson
1eb2bcea89 Removing custom xilinx primitives 
-Using the memory_sp macro instead...
-Cleaner design
-axi_elink now works!
 2015-05-21 22:54:29 -04:00
Andreas Olofsson
24d824f080 Fixing read response address 
-using `define from elink_regmap (ie 'D')
 2015-05-20 15:04:29 -04:00
Andreas Olofsson
7f0f858b92 Letting read response packets through 
-Needed for loopback testing
 2015-05-20 15:03:22 -04:00
Andreas Olofsson
a60de7fb30 Adding readback on axi_elink 
-Another cludgy memory
-Note that current esaxi doesn't support pushback so we have to hack the test to avoid read/write contention on this port.
 2015-05-19 23:53:05 -04:00
Andreas Olofsson
b1c3b3fb8c Adding filtering to ecfg_if 
-Avoids garbage writing coming back to esaxi
 2015-05-19 23:52:00 -04:00
Andreas Olofsson
005c9872dd Removing timeout from logic 
-Should be direct interface to esaxi
 2015-05-19 23:51:17 -04:00
Andreas Olofsson
7d524d0f68 Changing axi interface <--> elink protocol 
-Now consistant with packet, access, wait protocol
 2015-05-19 22:08:41 -04:00
Andreas Olofsson
8d3cbf8257 Clean axi_elink module 
-Clocks included inside for easy integration
-Another version might have the clocks and reset as inputs instead
 2015-05-19 22:07:16 -04:00
Andreas Olofsson
6d9731f14a Including environment for axi_elink 
-Should probably split this into separate environments
-Getting bulky and ugly...
 2015-05-19 22:06:15 -04:00
Andreas Olofsson
815db5669e Merge branch 'master' of https://github.com/parallella/oh 2015-05-18 15:39:42 -04:00
Andreas Olofsson
451a1fa925 MILESTONE: Bursts working!!! 
-Fairly clean minimalist design
-Complete redesign
-Need to do random read/write testing to make sure
-Speed?
 2015-05-18 15:38:30 -04:00
Andreas Olofsson
665876cfb4 Adding bursting to test bench 2015-05-18 15:37:46 -04:00
Andreas Olofsson
3ff0d56057 Deleting MIT license for now to avoid confusion. 
Everything is GPL until further notice
 2015-05-18 12:16:17 -04:00
Andreas Olofsson
41f97e45ff Converting to synchronous reset 2015-05-17 23:00:53 -04:00
Andreas Olofsson
ae8d4b4dcd Adding more reports 
-check_timing is a crucial summary
 2015-05-17 22:35:15 -04:00
Andreas Olofsson
559ffcc6e0 File name changes and additions 2015-05-17 22:34:42 -04:00
Andreas Olofsson
6485d1a9e7 Adding input delay constraints for RX 
-doesn't meet timing
-needs work...
 2015-05-17 22:33:42 -04:00
Andreas Olofsson
665af097c6 Name change 
-chip_resetb instead of resetb
 2015-05-17 22:32:39 -04:00
Andreas Olofsson
1ec8991e2a Adding IDELAY elements to xilibs 2015-05-16 22:07:17 -04:00
Andreas Olofsson
4fb6e7407c Integrating idelay elements in erx_io 2015-05-16 22:06:40 -04:00
Andreas Olofsson
017b72c37a MILESTONE: "almost final" block works! 
-bursting disabled, otherwise it looks good!
 2015-05-15 15:32:43 -04:00
Andreas Olofsson
d052da4ec9 Speed optimization 
-adding IDDR/ODDR blocks in IO
-still need to add the IDELAY controller and blocks
 2015-05-15 15:31:01 -04:00
Andreas Olofsson
9d3ecd0d06 Clock block cleanup 
-Moving TXCLK to CCLK domain, "feels cleaner"
-Also makes TXCLK independent of RXCLK
-So complete solution has a PLL and an MMCM
-Feeling is that the PLL for RXCLK could eventually be removed
-Need to add more state for locking clocks for receiver at end?
REVIEW!!!
 2015-05-15 15:28:19 -04:00
Andreas Olofsson
cd624d6531 Adding IDDR model 2015-05-15 15:27:45 -04:00
Andreas Olofsson
1f89e682bb Adding warning regarding clock divider 
-For now only div by 2/4/8 supported
-Really need to implement general purpose integer clock divider!
 2015-05-15 15:26:59 -04:00
Andreas Olofsson
ee363f6119 Fixed ODDR model for SAME_EDGE mode 2015-05-15 09:46:08 -04:00
Andreas Olofsson
836c4a65a8 Adding PLLE2_ADV model 2015-05-14 22:49:42 -04:00
Andreas Olofsson
a2d8c5c453 Adding PLL LOCK functionality 
-not accurate, but at least it gives some dunmy behavior for PLLLOCK
 2015-05-14 22:48:55 -04:00
Andreas Olofsson
02cc0f2b4f Adding reset to both sides of fifo 2015-05-14 22:47:25 -04:00
Andreas Olofsson
2e9744cd44 Changing default to simplify instantiation 2015-05-14 22:46:23 -04:00
Andreas Olofsson
35d86bcdc3 Adding pulse_stretcher circuit 
-simple but powerful for syncing from fast to slow clock domains
 2015-05-14 22:45:32 -04:00
Andreas Olofsson
007797169c Clock and reset interface changes 2015-05-14 22:43:44 -04:00
Andreas Olofsson
d2dcc15c52 Reset and clock cleanup 
-In the default mode we now have 7 input clocks to basic elink
-This is too many, need to simplify, not reasonable!
-But with all the knobs on the MMCM, performance will be great...
-WIP on bursting...
 2015-05-14 22:31:42 -04:00
Andreas Olofsson
77e210e7c2 Synchronous exit from reset 
-Async asert, sync deassert
-Haven't used this before.. (review?)
 2015-05-14 22:28:41 -04:00
Andreas Olofsson
d3d8f3f759 Clock and reset integration 
-moving clock and reset outside basic elink
-adding idelay reference clock
-separate and synchronized reset for each domain
-adding proper reset to fifo_cdc  (per domain, not asynch)
 2015-05-14 22:26:05 -04:00
Andreas Olofsson
1d848fe1d5 Making 2015-05-14 22:24:42 -04:00
Andreas Olofsson
5c690d38a1 Adding reset hardware state machine 
-concept developed by Gunnar Hillerstrom (VHDL)
-takes the driver out of the picture
-some people will run this bare metal
-more deterministic
-cuts down on hw/sw development issues
 2015-05-14 22:22:33 -04:00
Andreas Olofsson
a094f835c9 Rename (clarity) 
-file contains chip id, reset, and clocks
-base config driven by sys_clk
 2015-05-14 22:21:05 -04:00
Andreas Olofsson
befc18f368 MILESTONE: read/write works with all new RX/TX IO logic! 
-Fixes issue with back to back transactions!
-Read/writes work!!
-Needs more verification/analysis...
 2015-05-14 00:00:12 -04:00
Andreas Olofsson
4245c16b0d Adjusting phases for clocks 
-This is because the PLL model does not account for the input clock
-Actually a big dangerous cheat...
-How to model a PLL more accurately?
 2015-05-13 23:57:33 -04:00
Andreas Olofsson
58aeb0ee87 Adding warning message to ISERDES/OSERDES 
-Don't use them!!
 2015-05-13 23:33:26 -04:00
Andreas Olofsson
ade946ce90 Updating with new (and correct) modeling 2015-05-13 23:31:52 -04:00
Andreas Olofsson
4cd1e36537 Testbench update to include new clocking scheme 2015-05-13 23:30:30 -04:00
Andreas Olofsson
6ba45155fd Integrating clock approach change 
-clocks moved outside elink
-new packet interface format between protocol and io block
 2015-05-13 23:29:18 -04:00
Andreas Olofsson
b8c699fb22 Complete redesign 
-Communication with IO is with "packet format"
-No need to invent a 64 bit format just for stupid OSERDES
 2015-05-13 23:28:06 -04:00
Andreas Olofsson
af1f8a03eb Complete redesign 
-junking the old logic
-not needed with new IO approach
 2015-05-13 23:27:35 -04:00
Andreas Olofsson
0214df5804 Complete redesign of erx io logic 
-Building from primitives
-Work in progress, not quite complete
 2015-05-13 23:26:41 -04:00
Andreas Olofsson
9dcde59979 Complete redesign of erx 
-Giving up on ISERDES. No freaking proper documentaion and no open source simulation model.
-Rewriting io module with primitives.
-Looks like most of the logic disappears...
-Still work in progress
 2015-05-13 23:24:54 -04:00
Andreas Olofsson
89d54f4ed8 More flexible clock solution 
-moving clock block outside elink
-driving all key clocks into erx/etx
 2015-05-13 23:23:23 -04:00