9 Commits

Author	SHA1	Message	Date
Andreas Olofsson	9bc40a8355	Fixing wait issue ... -Removing the wait signal from the pipeline -Assumption is that the prog_full is used on fifo, allowing two entries to be captured in fifo. -May revisit this at some time...	2015-08-14 17:13:52 -04:00
Andreas Olofsson	ede8656081	Fixing mutual exclusive bug on receiver ... -When a read response is detected, there should be no spurious transactions to the RD/WR request fifos. -Move the "filter" backt to the erx_protocol block -Removed the remap bypass signal (was hacky) -Passes simulations again..	2015-08-14 15:37:37 -04:00
Andreas Olofsson	41f97e45ff	Converting to synchronous reset	2015-05-17 23:00:53 -04:00
Andreas Olofsson	81db0b7582	Completing elink hierarchy change ... -splits out clock domains -makes the core portion a clean/reusable module with defined interface	2015-05-10 23:38:08 -04:00
Andreas Olofsson	b2846c5312	MILESTONE: Read/write works back and forth ... -Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1 -Still not completely happy with reset (using async for now)	2015-05-04 17:13:51 -04:00
Andreas Olofsson	2460aa9247	Bypass erx remap on all ID matches ... Not just for read responses..	2015-04-28 16:58:05 -04:00
Andreas Olofsson	df53a2dc4f	Adding missing reset	2015-04-27 16:03:12 -04:00
Andreas Olofsson	4856e39193	RX address remap bug fix ... -Used the wrong sub vector... (silly mistake)	2015-04-27 09:29:22 -04:00
Andreas Olofsson	ea7683693c	Adding RX/TX address remapping ... The MMU is a monster and may be too much Adding simple remapping modules Covers todays feature and then some 1.) Static remapping 2.) Addresss compression	2015-04-24 17:29:05 -04:00