Andreas Olofsson
b2926fdc5e
Adding test for setting east link to half speed
2015-11-10 22:30:41 -05:00
Andreas Olofsson
d2d291a0fc
Merge branch 'master' of https://github.com/parallella/oh
2015-11-10 22:30:10 -05:00
Andreas Olofsson
7f0698bbc8
Fixed ctrlmode bug
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- Found this by trying to toggle the LED in hardware!!
- So freaking close!!
2015-11-10 22:29:30 -05:00
Andreas Olofsson
6b2f6f42bc
Added missing init() routine
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- Version 0 is the one currently in production, works!!!
- Now starting to debug the new linke (verion 1)
2015-11-11 02:00:14 +00:00
Andreas Olofsson
f92bcb3f0b
Adding elink register include file
2015-11-10 18:48:53 -05:00
Andreas Olofsson
8c4a02fbdf
Adding bringup script for elink
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- uses 104 bit packet for formatting
- makes for easy transition from verilog testbench
- happy with this one...
2015-11-10 17:01:04 -05:00
Andreas Olofsson
5840c3e369
Fixing reset bug
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- There is a register reset by out_clk reset on fifo_cdc
- This means the config path needs to us rx synched reset to be clean
2015-11-10 09:19:45 -05:00
Andreas Olofsson
f2b2c4fd00
Balancing TXclocks
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- Better to be balanced with clocks (BUFG) than trying with BUFIO and having CDCs. Tools warned about it...
2015-11-10 09:19:01 -05:00
Andreas Olofsson
04cd179f5a
Lint fixes for icarus/verilator
2015-11-09 21:57:25 -05:00
Andreas Olofsson
243ba6b608
Speedpath fix for rx io
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- reduce fanout on IDDR block
2015-11-09 21:56:46 -05:00
Andreas Olofsson
efef6448c2
Fixing wait bug on config write (2 bugs)
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- missing reset on wait signal
- missing wait on cfg
2015-11-09 21:55:46 -05:00
Andreas Olofsson
ef204a875b
Fixed register read/write test
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- Has been tested with dv_axi to work
2015-11-09 20:39:57 -05:00
Andreas Olofsson
02ae7cf83d
Cleanup
2015-11-09 20:39:48 -05:00
Andreas Olofsson
6dcd5e96bf
Cleanup after lock width change for zynq axi
2015-11-09 20:39:16 -05:00
Andreas Olofsson
e2c917b6f9
Fixed packet reformatting bug
2015-11-09 20:38:55 -05:00
Andreas Olofsson
497dd71aaa
Fixed readback bug
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- there were hard coded magic number in code, bad practice!
- now works!
2015-11-09 20:38:12 -05:00
Andreas Olofsson
13d29f8e67
Stupid typos..
2015-11-09 16:18:20 -05:00
Andreas Olofsson
61eb56c6f7
Final Vivado fixups:
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- reduced frame fanout, removed clock gater in erx_io (improves speed path)
- driving constants on "wid signals" (proper)
- making lock signal 1 bit wide to remove warning
- moved backed to BUFIO for IDDR blocks
2015-11-09 16:09:12 -05:00
Andreas Olofsson
55ba8ff635
Cleaning up warnings from FGPA tools
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- removing unconnected ports
- only one rst input for async_fifo
- synchronizing the reset input toe emaxi fifo
2015-11-09 13:23:40 -05:00
Andreas Olofsson
bf614a9873
Cleaning up fifo interface
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- removing redundant signals
- configuring to put synchronizer inside fifo
- one reset only (not two)
2015-11-09 13:20:46 -05:00
Andreas Olofsson
01fd24e069
Fixing synchronization reset speed path
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- This seems silly, why even have a syncrhonizer
- Safe to set speed path?
2015-11-09 00:16:35 -05:00
Andreas Olofsson
3797cac74f
Solving critical paths for TX/RX
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- Using the BUFIO makes another clock domain....FPGAs apparently hate clock domain crossings, avoid them at all cost.
- Now moving back to having on high speed clock domain for logic and DDR blocks, take care of IO alignment in software for TX and RX
- Also, fixed the io_wait path with logic...not sure what I was thinking there. Logic was trivial. The way it was,the io path was going straight into the FIFO as a wait.
2015-11-08 23:28:39 -05:00
Andreas Olofsson
65f772ddef
Fixing careless mistakes..
2015-11-06 22:51:09 -05:00
Andreas Olofsson
9383f32764
Making sure ETYPE is set to 0.
2015-11-06 22:41:43 -05:00
Andreas Olofsson
b6c95e5b94
Cleanup
2015-11-06 22:34:08 -05:00
Andreas Olofsson
5e18ed8c52
Making defines unique
2015-11-06 22:33:33 -05:00
Andreas Olofsson
63bf5d25a4
Moving to active low reset
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- Because this is the right thing to do for chips
- Not going to tell you why...
2015-11-06 16:51:57 -05:00
Andreas Olofsson
3969e6d19e
Moving to MIT license
2015-11-06 11:25:05 -05:00
Andreas Olofsson
8b2974feae
Massive reorg!
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- flattening hierarchy
- removing junk
2015-11-06 10:59:22 -05:00
Andreas Olofsson
e47fd56a21
Bulk edits (clean up later)
2015-11-06 07:03:28 -05:00
Andreas Olofsson
5086052cb5
Adding timing constraints
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- structure feels right
- one folder per reusable module
- everything should be contained within one "package"
2015-11-04 22:13:35 -05:00
Andreas Olofsson
81fe46a929
Removing xpr file
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(everything done through tcl)
2015-11-04 22:12:50 -05:00
Andreas Olofsson
025af1ee54
Yay! Now runs to completion
2015-11-04 22:11:19 -05:00
Andreas Olofsson
ee6a9a93ac
Updating scripts
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- adding more compatibility families
2015-11-04 21:46:15 -05:00
Andreas Olofsson
92272e211d
Adding missind dirs in comamnd file
2015-11-04 20:04:44 -05:00
Andreas Olofsson
6a423b5999
Improcing mmcm/pll clock path
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-apparantly the BUFG in the feedback was not liked by the P&R
2015-11-04 20:02:45 -05:00
Andreas Olofsson
8938c396b6
Merge pull request #15 from peteasa/packagingPathUpdates
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Updated paths and added missing source
2015-11-04 17:57:49 -05:00
Andreas Olofsson
30077cc1e5
Scripted elink build script (version 0)
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- starting to feel better about structure
2015-11-04 17:53:54 -05:00
Peter Saunderson
9009113162
Updated paths and added missing source
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Signed-off-by: Peter Saunderson <peteasa@gmail.com>
2015-11-04 20:14:57 +00:00
Andreas Olofsson
6b83cdb0d7
Testbench bug fix
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- can't connect a 64 bit interface to a 32bit one...
- (abuse of emaxi..)
2015-11-03 21:50:26 -05:00
Andreas Olofsson
f849f2410f
Adding infrastructure for axi_elink
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- Need to clean up some of these files later
2015-11-03 19:52:08 -05:00
Andreas Olofsson
36b0f14ca5
"Fixing" wait signal
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- Giving a wait on every ack just doesn't make sense on the read port with a fifo there??
- Makes for a nasty combinatorial loop during integration.
- Test passes (but need to look into this more)
2015-11-03 19:49:38 -05:00
Andreas Olofsson
6114471935
Adding active signal to interface
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- kind of like "pll lock"
2015-11-03 19:49:09 -05:00
Andreas Olofsson
b4daf73157
Optimizing clock path
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* Sven's help!
* Better to use bufio to keep all paths internal, more determenistic path
2015-11-03 14:15:09 -05:00
Andreas Olofsson
fb45666b13
Adding idelay config register documentation
2015-11-03 10:46:05 -05:00
Andreas Olofsson
d7bf1389d6
Changing idelay bit map
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- the 5 bit fields was driving me nuts!
- always work in nibbles, place the msb elsewhere (or work with 16 bit values)
2015-11-03 10:31:06 -05:00
Andreas Olofsson
275ed5252f
Adding test for sweeping idelay and testing reads
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-It works!!!!
2015-11-03 10:30:20 -05:00
Andreas Olofsson
971b591454
Shifting first byte of packet down by one bit to accomodate new format
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- this of for future proofing
2015-11-02 20:51:35 -05:00
Andreas Olofsson
02b22a36f3
Fixing test to conform to new stimulus format
2015-11-02 20:51:03 -05:00
Andreas Olofsson
2b67e0007a
Updated simulation instructions
2015-11-02 19:28:00 -05:00
