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659 Commits

Author SHA1 Message Date
Andreas Olofsson
d14cc0f258 Added missing burst bit for legacy elink...
- This is a pain in the ass and should never have been implemented in the first place!
- Burst information is contained in two places, once in the first byte being transmitted and once by the frame staying high
- This was done because there was a second special bursting mode where data is streamed into the same address, so bit[2] becomes a "command bit".
2015-11-17 09:46:22 -05:00
Andreas Olofsson
ebc55fa0ab Adding random transaction generator
!!found critical bug in design!!
2015-11-16 22:02:44 -05:00
Andreas Olofsson
2f9e2910ac Fixing 64 bit read bug 2015-11-16 22:01:45 -05:00
Andreas Olofsson
3102d6cd44 Adding comments 2015-11-16 09:58:47 -05:00
Andreas Olofsson
51c8ae600d Burst works (really this time!!!)
-Solved a speed path in synchronizing the wait signal, had to use the first edge signal fo the IO and the lclk_div4 for the core logic. It seems that the FPGA has a really hard time mixing clock domains, the routing delay between domains explodes
-Put in some special case logic for edge cases, like when there is a wait coming in from the IO and there is a wait from the IO. In that case, the packet gets sampled by the IO and not by the current logic.
-This needs to be cleaned up eventually, not clean enough but it's good enough for now.
2015-11-16 00:42:34 -05:00
Andreas Olofsson
5197822f53 Fixing burst logic speed path
- The burst signal was going fro lclk_div4 domain straight into the io high speed domain. There is quite a bit of logic on this signal. Instead of starting with false paths or multi cycle paths with firstedge, I changed the pipeline.
2015-11-15 12:26:54 -05:00
Andreas Olofsson
f77938e9b0 Simplifying TX logic!!!!
- The logic was a mess, causing me to go around in circles for days. In the end, by adding a missing sync circuit (duh!) between the fast and slow clock to align the edges and removing a redundant pipeline stage ("double") the nasty logic just fell away. Looks good now.
-Write bursts mostly works and design looks clean.
-one bug left to fix on streams of writes...
2015-11-15 01:35:46 -05:00
Andreas Olofsson
431abcda57 Removing write decode from wait pushback 2015-11-15 01:35:04 -05:00
Andreas Olofsson
df0deabd0f Re-re-fixing the wait on RX
- (fixing a temporary bad commit)
2015-11-15 01:34:20 -05:00
Andreas Olofsson
4b384be602 Fixing edge align circuit
- duh error
- making output positive edge aligned, the negedge nastyness should be maintained within module...
2015-11-14 23:33:48 -05:00
Andreas Olofsson
e70c51670c Adding edge align circuit 2015-11-14 22:41:19 -05:00
Andreas Olofsson
75710f25b7 Simplifying wait logic 2015-11-13 22:47:46 -05:00
Andreas Olofsson
c1beed9a13 Two more wait bugs for burst
- The burst signal needs to be pipelined like everything else (0th order..)
- Don't look at write signal when pushing back wait...WILL GO BACK AND REVISIT THIS ONE LATER.
- Yeah, burst write test now passes!!!!
2015-11-13 17:26:05 -05:00
Andreas Olofsson
52b328c194 Redesign of elink transmitter
- Old design was not workable with bursting and long waits. The wait signal needs to be very carfully handled since it's asynchronous to the clock.
-The TX needs to be stopped quickly so the sync needs to be done at the high speed clock, not at div4 clock
-Since there are synchronizers here, there should be only one point of sync. This is not completely the case still, but I think??? it should be safe by constructiona at this point.
-bursting working at this point for writes!!!!!
2015-11-13 16:31:59 -05:00
Andreas Olofsson
78a72aa428 fixing packet format for remap block 2015-11-13 16:31:29 -05:00
Andreas Olofsson
a335194dea fixing packet reshuffling bug 2015-11-13 16:30:33 -05:00
Andreas Olofsson
f7806821c7 Various wait cleanups in RX
- using rx reset, safer as this stays in reset longer, until the clock has hade time to clean up the rest
2015-11-13 16:28:40 -05:00
Andreas Olofsson
4637f90546 Fixing wait circuit in dut (randome wait gen was removed from top) 2015-11-13 16:27:06 -05:00
Andreas Olofsson
fbcf58d642 Adding description for wait signal
- Also fixing packet description
2015-11-13 16:26:32 -05:00
Andreas Olofsson
75cef84075 Timescale stuff
- Need to look into this again, gotchas here
-
2015-11-13 16:25:38 -05:00
Andreas Olofsson
9dbaeaedcd adding hello world test for elink, always run this first 2015-11-13 16:24:59 -05:00
Andreas Olofsson
c725f5cab6 Fixing memory model for emesh
- Moving random wait generator into module
- Fixing wait circuit
2015-11-13 16:23:30 -05:00
Andreas Olofsson
13c523e80c Fixing wait circuit in emmu
- need to consider read/write
- fixing packet parsing, write bit was moved o [0]
2015-11-13 16:22:23 -05:00
Andreas Olofsson
a44778b8be Putting all ip generator blocks in one repo 2015-11-13 16:21:53 -05:00
Andreas Olofsson
24afa3c9a0 Deleting old files 2015-11-12 11:00:23 -05:00
Andreas Olofsson
3f1296b099 Cleanup 2015-11-12 10:50:05 -05:00
Andreas Olofsson
847eae23ab Adding proper read alignment for ememory model
-Byte/shorts now work
2015-11-12 10:49:40 -05:00
Andreas Olofsson
8820c8500a Adding wait circuit for axi/elink 2015-11-12 10:47:52 -05:00
Andreas Olofsson
3b2968f162 Clean up test files 2015-11-12 10:46:52 -05:00
Andreas Olofsson
a44053fbe1 Adding Xilinx behavioral models for fifo 2015-11-12 09:57:55 -05:00
Andreas Olofsson
60bdda4dfa Dead simple test 2015-11-12 00:59:21 -05:00
Andreas Olofsson
a9e034bef9 Bringing access low during wait 2015-11-12 00:58:06 -05:00
Andreas Olofsson
07dff85090 Changing build script to work with xilinx model 2015-11-12 00:56:02 -05:00
Andreas Olofsson
4bd164bae4 Giving up..adding fifo generator model from xilinx 2015-11-12 00:55:01 -05:00
Andreas Olofsson
00c7aa6dcf Fixing model bug for prog_full
-I really need to fix this properly...
2015-11-11 22:35:03 -05:00
Andreas Olofsson
1dcd9a82bd Fixing burst transmit bug
- The burst should be interrupted as soon as there is a wait signal. When the wait stops, a new frame naturally starts.
2015-11-11 22:33:54 -05:00
Andreas Olofsson
fa5011937c Taking away prog_full from wr_en
- The point of prog_full is to give us some slack..
2015-11-11 22:32:21 -05:00
Andreas Olofsson
4a7b0d8f1c Adding proper test or bursting
- Need to at a minimum try to fill the fios
- Need to add a wait circuit at the back end of fifo to test pipe
2015-11-11 22:28:53 -05:00
Andreas Olofsson
547bf9751f Adding a utility for generating emesh transactions 2015-11-11 18:13:52 -05:00
Andreas Olofsson
9ada08a42c Adding parallella.bit.bin 2015-11-11 14:28:38 -05:00
Andreas Olofsson
dccaadc286 Updating register names and fixing error in description of RXCFG 2015-11-11 14:26:46 -05:00
Andreas Olofsson
1ddbc4c0a8 Adding missing register 2015-11-11 14:26:35 -05:00
Andreas Olofsson
038d39def7 Defparam typo
- Not caught by iverilog!! (file bug??)
- Caught by Vivado.
2015-11-11 14:13:38 -05:00
Andreas Olofsson
867b750c50 Adding write from stimulus to dv link1
- also, more cleanup of ID parameters
2015-11-11 14:02:02 -05:00
Andreas Olofsson
c885745f6c Fixing half/byte zero-out bug
- Interrupted mid coding apparently..
- Upper bits need to be zeroed out for 8/16 bit read responses
2015-11-11 14:00:13 -05:00
Andreas Olofsson
d788e0da2d Fixing alignment issue on write
-The epiphany chip memory does alignment on write
2015-11-11 13:59:24 -05:00
Andreas Olofsson
4885c3f7d2 Adding byte/halfword test 2015-11-11 13:58:55 -05:00
Andreas Olofsson
0a2ea66b7e Bug fix. Adding missing ID parameter.
- would only show up at different ID
- better to always make defauly nonsense
- sneaky...
2015-11-11 13:58:04 -05:00
Andreas Olofsson
9c1fb038a9 Adding test for remapping logic 2015-11-11 13:57:18 -05:00
Andreas Olofsson
3f0efb9db2 Adding dummy.elf for bootgen 2015-11-11 13:56:48 -05:00