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898 Commits 7 Branches 1 Tag
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24 Commits

Author SHA1 Message Date
Andreas Olofsson
fd7aff5dd8 Fixing warning messages in chip synthesis tool 
- Don't fight the tools
- No way to remove these warnings and I don't want to have to tell everyone to include maging "don't output this kind of warning flags" that are global to a project...that's just bad practice.
- Didn't take many minutes to remove these warnings and now synthesis runs through with 0 warnings ... much cleaner.. inspires more confidence
 2016-02-12 11:04:52 -05:00
Andreas Olofsson
b516a2cebf Contributing nested interrupt controller 2016-02-11 22:04:36 -05:00
Andreas Olofsson
0804d8ea29 Fixing weird Vivado error 
-Seems vivado doesn't like the "|=" operation??
 2016-01-20 21:45:55 -05:00
Andreas Olofsson
1e35436b10 Adding generic mesh packet mux 2016-01-20 17:14:55 -05:00
Andreas Olofsson
a68bba1572 Cleaning up register interface 
- Removed the cfgif block, too confusing. There is a good lesson here. Probably the n'th time I that I have been overzealous about reuse. When you end up adding a parameter to a block that duplicates the logic 2X it's always better to create two separate blocks...
- Changed the register access interface to packet format
- Change the priority on the etx_arbiter to pick read responses first
- Removed redundant signals
- Took away the read resonse bypass on remap in tx for now..
- Removed defparams (convention)
- Unified wait signal on tx
- Fixed cfg wait
-
 2016-01-11 17:35:53 -05:00
Andreas Olofsson
152ee815e3 Making default 32bit for ease of use 2016-01-11 15:04:20 -05:00
Andreas Olofsson
8b257066b3 Adding 64-bit support in packet format 2016-01-10 11:50:23 -05:00
Andreas Olofsson
167744d7a9 Fixed data width 2015-12-17 12:52:49 -05:00
Andreas Olofsson
dbd8cd8044 Adding common module for write alignment 2015-12-17 12:37:41 -05:00
Andreas Olofsson
79c312d166 Cleanup 2015-12-17 12:36:02 -05:00
Andreas Olofsson
3708417934 Reuse refactoring 
-Made AW primary parameter to make reuse possible with other design
-Insert TARGET_SIM ifdef to make design synthesizable
 2015-12-17 12:34:32 -05:00
Andreas Olofsson
27d7b0ed7c Cleaning up code 2015-12-17 12:34:03 -05:00
Andreas Olofsson
2a70178f47 Changing core parameter of packets 
-Address width is a more natural primary component
 2015-12-17 12:33:19 -05:00
Andreas Olofsson
71b467728d Making mux parametrized 2015-12-07 11:19:12 -05:00
Andreas Olofsson
19fa611bb9 Massive reorganization to impove reuse 
- adding more chip code
- pushing memory stuff into common
- making common "oh_" naming class
-
 2015-11-30 13:45:49 -05:00
Andreas Olofsson
847eae23ab Adding proper read alignment for ememory model 
-Byte/shorts now work
 2015-11-12 10:49:40 -05:00
Andreas Olofsson
3969e6d19e Moving to MIT license 2015-11-06 11:25:05 -05:00
Andreas Olofsson
e47fd56a21 Bulk edits (clean up later) 2015-11-06 07:03:28 -05:00
Andreas Olofsson
6d9d9702d8 Simulation file cleanup 2015-11-03 19:53:43 -05:00
Andreas Olofsson
46687fe7fd New packet format 
* Removed acess at bit [0], was redundant...
* Frees up one more bit for ctrlmode
 2015-11-02 20:52:27 -05:00
Andreas Olofsson
22714f3d9d Adding new emesh format files 
* Adding an improved monitor file
* Adding mesh interface (avoids crud logic at top level)
* A emesh packet memory module
 2015-11-02 16:14:08 -05:00
Andreas Olofsson
c627827a6b Fifo cleanup 
-Adding model (one source..)
-generate for 104x32 for xilinx
-making prog_full the default full indicator
-bringing out almost_full for future use
-fixing interface change in all modules
 2015-07-02 16:59:38 -04:00
Andreas Olofsson
bba7511f15 Fixing syntax errors caught in synthesis 2015-05-06 12:27:13 -04:00
Andreas Olofsson
a36875ac09 Adding basic emehs transaction generator 
-Replace with DMA...
 2015-05-05 21:39:20 -04:00