FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-17 20:02:53 +08:00
Code Issues Projects Releases Wiki Activity
1,369 Commits 7 Branches 1 Tag
Commit Graph

1369 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Andreas Olofsson
383cda2550 Adding preliminary r5 opcodes 2016-09-26 15:16:00 -04:00
Andreas Olofsson
5a583c598c Adding buffer 
- Sometimes you need to instatiate buffers manually in RTL to get around some absolutely braindead behaviour in eda tools. Not often, but sometimes...
 2016-09-03 14:59:30 -04:00
Andreas Olofsson
70533b57b0 Refactoring asic code 
- remove redundant hierarchy
- using shorter/better names to make sdc constraints less ugly
 2016-09-03 14:40:51 -04:00
Andreas Olofsson
94469ed5f4 Resetting shift register 
- Less red to look at...
 2016-09-03 14:40:21 -04:00
Andreas Olofsson
a306aa5178 Removing one level on redirection on clockor 
- It was getting annoying....
 2016-09-02 00:39:32 -04:00
Andreas Olofsson
128c4015b3 Adding reset to wakeup pipeline 
- Suspect behaviour when clock is absent..
 2016-09-01 19:32:48 -04:00
Andreas Olofsson
0f8beea513 Fixing reset bug for MIO emode 
- Shows up when there is no free running clock. Don't assume there is a clock at startup!
 2016-08-28 19:14:45 -04:00
Andreas Olofsson
3e18d921d6 Adding DV hook into SPI block 
- Inputting large amount of data through SPI in DV is soooo painfully slow. Added hook to speed up development. 100x speedup in verification time-->100x speed up in design team.
 2016-08-26 23:50:05 -04:00
Andreas Olofsson
dc22df0d5c Fixing MIO synthesis errors/warnings 2016-08-26 00:41:42 -04:00
Andreas Olofsson
a13b665027 SPI synthesis cleanup 2016-08-26 00:40:09 -04:00
Andreas Olofsson
ac735cba6a Fixing MIO emesh transaction bug 
- data should go straight into fifo for first cycle
- after that, the data is taken from a temporary buffer
 2016-08-25 21:01:44 -04:00
Andreas Olofsson
073d003e40 Fixing MIO transmit DDR mode 
-iowidth refers to the size of a single ended bus
-DDR is implicitly half that size
 2016-08-25 21:01:01 -04:00
Andreas Olofsson
ebeeb1dd8b Fixing bug in MIO receiver 
-nibble wide io now supported in RX
 2016-08-25 21:00:34 -04:00
Andreas Olofsson
c566f46a60 Adding missing parameter in MIO 2016-08-25 17:53:02 -04:00
Andreas Olofsson
988d4dbd94 Fixing MIO mode switch bug 
- Need to look over this circuit again, feels nasty. There is a ever rotating state here, that should probably be reset when there is no transaction, but how?
 2016-08-25 17:29:55 -04:00
Andreas Olofsson
a65bfafbb6 Fixing MIO DDR mode 
Works!
 2016-08-25 17:29:29 -04:00
Andreas Olofsson
ae8264afc1 MIO interface changes cleanup 2016-08-25 15:43:55 -04:00
Andreas Olofsson
c9046cd645 Implementing amode/emode receiver 
-emode debugged, working!!
 2016-08-25 15:43:27 -04:00
Andreas Olofsson
ae24a4754c Changing to datamode in rx 
- More standard
 2016-08-25 15:42:48 -04:00
Andreas Olofsson
97ef662e38 Fixing various simple MIO receiver IO bugs 
- Really a nice reverse of TX logic...
- Support for partially full transfers when frame goes low
 2016-08-25 14:15:40 -04:00
Andreas Olofsson
401b0a64f9 Connecting missing clock 2016-08-25 14:15:25 -04:00
Andreas Olofsson
5ee15b4802 Fixing default config for new register file 2016-08-25 12:40:29 -04:00
Andreas Olofsson
75267a539e Fixing bugs in transmit logic 
- Serializer wait was missing
- Need to reload on last cycle before emptying to avoid stall, need "next"
 2016-08-25 12:39:16 -04:00
Andreas Olofsson
e36519138a Adding extra cycle to make number of bytes even 
- Needed for ddr operation
- Enables IOW=16 for sdr mode
 2016-08-25 12:38:34 -04:00
Andreas Olofsson
ac90486cb1 New MIO interface 
- Work in progress, compiles but not yet debugged
 2016-08-25 11:57:28 -04:00
Andreas Olofsson
f560a5fc20 Adding iowidth as dynamic parameter for MIO 2016-08-25 11:56:42 -04:00
Andreas Olofsson
f6cb0bb7bf Redesigning MIO rx 
- Standardize on 64bit FIFO interface
- Stuff bytes into shifter register before transferring to fifo
- Use valid bits per byte to keep track of valid data through pipe
- Work in progress...
 2016-08-25 11:55:06 -04:00
Andreas Olofsson
1b24fabe15 Adding missing wait signal to rx 2016-08-25 11:54:54 -04:00
Andreas Olofsson
9919a34c44 Adding iowidth as parameter to MIO 2016-08-25 11:54:36 -04:00
Andreas Olofsson
9e7e771898 Fixing non-blocking bug in dv 2016-08-25 11:45:20 -04:00
Andreas Olofsson
bfb03e31b3 Fefactoring to clarify register usage 2016-08-25 11:44:30 -04:00
Andreas Olofsson
4354a46dce Adding new fifos for MIO 
-In preparation for redesign
 2016-08-25 11:43:48 -04:00
Andreas Olofsson
290da8ce48 Adding missing reset synchronization 2016-08-25 11:42:31 -04:00
Andreas Olofsson
e51d628ed4 SPI code cleanup 2016-08-25 09:02:14 -04:00
Andreas Olofsson
4c6cdcaf74 Fixing nasty glitch bug on clock 
-Created phantom event simulator
-Lucky to catch it quickly
-Don't know wtf i was thinking with that circuit...
 2016-08-24 01:14:05 -04:00
Andreas Olofsson
f7ce7b800c Fixing spi controller 
- Manually merging work from @olajep in PR #85 (too far out of sync)
- Fixing issue with lsbfirst logic
- Adding logic for manual control of slave select
- Fixing status register for polling reads
- Still a timing/glitch issue on mosi, fix it later...
 2016-08-24 00:20:51 -04:00
Andreas Olofsson
f4a74b462f Adding manual control of slave select pin 2016-08-24 00:19:46 -04:00
Andreas Olofsson
b9a9853753 Linking test file, copying around sources is really bad... 2016-08-24 00:18:25 -04:00
Andreas Olofsson
e5b35f611e Merge pull request #96 from peteasa/AugFixes 
Aug fixes
 2016-08-23 18:15:05 -04:00
Andreas Olofsson
fa7d6f7c2e Changing latching responsibility in clock mux 
- Ugly to put latch inside the clock mux, there are situations when there is no clock. Need to have complete control over reset and sampling clock, so better to put latch outside of the clock mux..more legoish..
 2016-08-23 17:27:17 -04:00
Andreas Olofsson
80c4221b14 Merge branch 'master' of github.com:parallella/oh 2016-08-23 17:15:03 -04:00
Matt
7e80a82547 oh_add: Fix typo in the function description 
Fixes a small typo in the description of the adder-subtractor (two's complement representation).
 2016-08-21 17:02:46 +02:00
Peter Saunderson
a8ef3748bd AXI: emaxi: added nreset to instantiation of oh_dsync 
Signed-off-by: Peter Saunderson <peteasa@gmail.com>
 2016-08-17 15:57:25 +01:00
Peter Saunderson
e781f39e5e TARGET changed back to XILINX from GENERIC 
Commit 3fa5fce "Cleaning up fifos" accidentally changed TARGET from XILINX to GENERIC
This commit fixes this problem and moved TARGET assignment to the top level
Fixes CRITICAL WARNING: [Designutils 20-1280] Could not find module 'fifo_async_104x32'.

Signed-off-by: Peter Saunderson <peteasa@gmail.com>
 2016-08-17 15:30:38 +01:00
Peter Saunderson
553ee31400 Synthesis: parameter = `CFG_ASIC not accepted in module declaration 
Vivado does not pre-process defines in the module declaration.
The result is that each module with this type of declaration is AutoDisabled by Vivado

Moving the top level define to a localparam fixes this problem

Signed-off-by: Peter Saunderson <peteasa@gmail.com>
 2016-08-17 15:06:01 +01:00
Peter Saunderson
55118cee9d Apply CFG_ASIC at the top level 
Commit 381ba09 adds CFG_ASIC as a primary variable.  This commit
allows this to be set in the system_build.tcl script at build time


Signed-off-by: Peter Saunderson <peteasa@gmail.com>
 2016-08-17 14:22:04 +01:00
RainerWasserfuhr
b9b42bd93e fixed sort order 2016-08-05 21:49:20 +02:00
Andreas Olofsson
aac3d5b3a2 Synthesis cleanup 2016-07-24 05:11:47 -04:00
Andreas Olofsson
67409dba7a Simplifying names to make it easier to specify generated clocks 2016-07-09 20:32:57 -04:00
Andreas Olofsson
2c272e7afa Synthesis cleanup 
- adding missing reset on pulse/edge detectors
- disconnecting unused signals in spi clockdivider
- changin output to input on spi_slave_io for read data
 2016-07-09 20:31:00 -04:00