Andreas Olofsson
c627827a6b
Fifo cleanup
...
-Adding model (one source..)
-generate for 104x32 for xilinx
-making prog_full the default full indicator
-bringing out almost_full for future use
-fixing interface change in all modules
2015-07-02 16:59:38 -04:00
Patrik Lindström
634ff371ac
Bug fixes
2015-06-30 13:32:05 +02:00
Andreas Olofsson
b2b7f96e86
Making FIFO/memories easier to use
...
-WIDTH/DEPTH parameters
-Removing references to "clean" in ifdefs
2015-05-07 23:50:34 -04:00
Andreas Olofsson
b2846c5312
MILESTONE: Read/write works back and forth
...
-Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1
-Still not completely happy with reset (using async for now)
2015-05-04 17:13:51 -04:00
Andreas Olofsson
b375aaeb07
Adding back emesh access
...
-Write from emesh, read from mi.
-Final decision?
-Make readback 64 bits.
2015-05-04 10:36:07 -04:00
Andreas Olofsson
1c14ccd5d9
Generalizing emailbox
...
-There should be two clocks
(even though there is only one clock in erx)
2015-05-01 17:34:04 -04:00
Andreas Olofsson
395a1b3cb7
Merge branch 'master' of https://github.com/parallella/oh
...
Adding complete register documentation
Conflicts:
elink/README.md
2015-04-29 11:55:01 -04:00
Andreas Olofsson
f544c44a08
Adding register access from RX
...
-Access without symmetry was awkward, now we can reach regs from TX or RX side
-Removes a special path for mailbox (came for free)
-At the same time reduced clock complexity (one clock for system!!)
-Moved mailbox to top level
-Changed main clock to "sys_clk" for all
2015-04-27 23:51:00 -04:00
Andreas Olofsson
c0d8c967c4
Address remapping integration
...
Integrated remapping logic (compiles)
Starting debug tomorrow...
2015-04-24 17:39:05 -04:00
Andreas Olofsson
370034437f
Added proper 64bit write port to mailbox
2015-04-23 23:14:04 -04:00
Andreas Olofsson
0f0ff55928
Verilator based lint cleanup
2015-04-23 18:57:55 -04:00
Andreas Olofsson
31e721cea7
Interface change
...
Changed to packet interface
Changed name to "mailbox"
2015-04-23 17:54:59 -04:00
