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1,431 Commits 7 Branches 1 Tag
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203 Commits

Author SHA1 Message Date
Andreas.Olofsson
d7769070fc Adding diff and sticky flag to ease debugging 
-One flag for end of test pass fail
-Seond flag for gtkwave to see where all the fails happen
 2020-07-27 19:56:57 -04:00
Andreas.Olofsson
7abc91751a Fixing basic register file bug 
-Working in simulation but was not synthesizable by DC
 2020-07-27 19:56:11 -04:00
Andreas.Olofsson
9147a49103 Fixing basic carry bug in the csa4:2 
(carry was wrong)
 2020-07-20 22:51:58 -04:00
Andreas.Olofsson
ae6cdc912e Mapping cs42 to csa32 
-Better synthesis results
 2020-07-20 14:50:09 -04:00
Andreas.Olofsson
9ac530e526 Adding indication that test started for regression clarity 2020-07-19 10:12:07 -04:00
Andreas.Olofsson
84e8449cb5 Moving sampling to negedge for clarity 2020-07-14 13:50:24 -04:00
Andreas.Olofsson
126f859908 Adding clock enable for register 
-Removing the ASIC CFG as well...have to rethink that concept, not really working
 2020-07-14 13:48:42 -04:00
Andreas.Olofsson
d7639390f4 Typo fix 2020-04-23 22:44:47 -04:00
Andreas.Olofsson
58eedb914d Cleanup 2020-04-22 23:17:25 -04:00
Andreas.Olofsson
7c0e1bc01f Adding fail criteria to common simulation control infrastucture 
-Preparing for CI and unit tests for all modules
 2020-04-22 23:16:43 -04:00
Andreas.Olofsson
2c106bed5e Moving checker to positive edge 
-This should be synthesizable into FPGAs!
 2020-04-22 23:15:41 -04:00
Andreas.Olofsson
a7870ac9de Cleaned up counter 
-Not functional
 2020-04-22 23:15:12 -04:00
Andreas.Olofsson
d8d2d0c20e Changing dv_checker to oh_simchecker 
-library consistency
 2020-04-22 22:40:43 -04:00
Andreas.Olofsson
cf47e56436 Changing dv_* to oh_* to be consistent 2020-04-22 21:52:37 -04:00
Andreas.Olofsson
d9897a1bec Multi-type multiplier working 
-only reference model implemented
-Next, implement complete algorithm and output partial products
 2020-04-09 21:42:28 -04:00
Andreas.Olofsson
d6b6e1bd76 Adding basic multiplier stub 2020-04-09 14:58:29 -04:00
Andreas.Olofsson
97bc8d08af Name change one last time... 2020-04-07 10:25:54 -04:00
Andreas.Olofsson
8b39f7e444 Fixing register file 
-Changing DW to RW (RW not always equal to DW..)
-Blocking rd_data on valid
-Fixing elemetary bugs based on indices
-Simplifying index code
-Add configurable pipeline stage?
 2020-04-07 10:23:35 -04:00
Andreas.Olofsson
68829c93d0 Adding dumpvar to interface 2020-04-02 22:14:07 -04:00
Andreas.Olofsson
32b103d290 Adding parametrized register file 2020-04-02 22:13:07 -04:00
Andreas.Olofsson
18bb820f56 Merge branch 'master' of github.com:aolofsson/private-oh 2020-03-28 15:40:11 -04:00
Andreas.Olofsson
c271360709 Changing order of RAM array 2020-03-28 15:38:29 -04:00
Andreas.Olofsson
281a19d7bf Adding debug features to fifo_sync 
-Ability to dump array
-Error on attempt to write to fifo while full
 2020-03-26 12:24:45 -04:00
Andreas.Olofsson
5269354461 Adding ability to dump array for iverilog 
-Important for FIFO debugging
 2020-03-26 12:24:01 -04:00
Andreas.Olofsson
064ec792d3 Adding testname to simplfy grepping of regression suite results 2020-03-26 12:22:56 -04:00
Andreas.Olofsson
7b33ff0405 Fixing yet another fifo bug... 2020-03-20 20:39:15 -04:00
Andreas.Olofsson
3c8be0c083 Fixing brain-dead bug! 
-I guess nobody has been using this fifo, because it was hoplessly broken. Fucking sad.
 2020-03-13 12:24:35 -04:00
Andreas.Olofsson
bee941aa61 Adding reset wakup event to standby module 
-Create an event at rising edge of reset
-Turn on the clock for long enough to allow for reset signal to get turned on
-Note the race here! This is why the rest and standby needs to be combined into one block.
 2020-03-13 11:05:49 -04:00
Andreas.Olofsson
412fb61519 Changing delay function to take a clock 
-The combinatorial delay elemement doesn't belong in this library, too specific!
 2020-03-13 11:04:08 -04:00
Andreas.Olofsson
04675f49a7 Adding synchronous clear signal to fifo 
-It's not uncommon to want to clear/invalidate all entries int he FIFO
-Still need async reset for power-on in absence of clocks
 2020-03-13 11:02:49 -04:00
Andreas.Olofsson
2b2c719765 Fixing another bug (PS vs N) 2020-03-04 21:12:24 -05:00
Andreas.Olofsson
4f0f81997e Fix datagate bug! 
-Was not turned on at all! Alwats on
 2020-03-04 18:36:38 -05:00
Andreas.Olofsson
069681ca6a Typo fix in dv_ctrl 2020-02-17 07:43:41 -05:00
Andreas.Olofsson
a09374d74b Adding FAIL timeout condition in test 2020-02-15 21:58:17 -05:00
Andreas.Olofsson
c04523503e Making stimulus configurable 
-ability to turn off timesetamps dynamically
-ability to ignore valid signal
 2020-02-06 12:50:34 -05:00
Andreas.Olofsson
9e9d323025 Changing the CFG_ASIC approach 
-Should be ifdef, since this is a global. You will never be doing and not an asic at the same time!
 2020-02-04 23:04:52 -05:00
Andreas.Olofsson
21349445ef Change macro name to reduce confusion 2020-02-04 22:43:18 -05:00
Andreas.Olofsson
ca3c01144f Changing stimulus order to avoid on memh 2020-02-04 22:42:41 -05:00
Andreas.Olofsson
f7012f8369 Basic memh based stimulus file. 
-Much cleaner than previous work!
-Allows for loading into FPGA!
 2020-02-03 13:19:55 -05:00
Andreas.Olofsson
1bd7c552fb Adding basic tesbench for stimulus function 
-testing the tester
 2020-02-03 13:19:21 -05:00
Andreas.Olofsson
b23a63e2ba Adding firmware example for readmemh 2020-02-03 13:16:37 -05:00
Andreas.Olofsson
b057d47d57 Duh, fixing CFG_ASIC issue! 
-It's a global, use ifdef to avoid compilation issues
-No need for generate
 2020-02-02 23:12:19 -05:00
Andreas.Olofsson
e017f0f290 Stimulus write port written 
-Read port half done, looks straight forward
 2020-02-02 23:11:29 -05:00
Andreas.Olofsson
c23862f4a6 Starting general purpose design of stimulus! 
-memory based, generic
 2020-02-02 21:35:15 -05:00
Andreas.Olofsson
7bd980fca2 Adding include directorys to lib.cmd 2020-02-01 09:07:47 -05:00
Andreas.Olofsson
d6f5de24d7 Changing hierarchy to promote blocks 2020-01-28 18:12:57 -05:00
Andreas Olofsson
7094173ae9 Reorg! Why? 
- The top level directory was not scaling, too imposing
- Friendlier to download a repo and see a finite number of top level dirs
- We are just getting started...
 2016-03-22 08:13:40 -04:00
Andreas Olofsson
a6f1dc8971 Merge branch 'master' of github.com:parallella/oh 2016-03-22 08:01:04 -04:00
Andreas Olofsson
85ecd25268 Remving the ugly wait hack in the stimulus, not the way to drive the pipeline 2016-03-21 20:51:35 -04:00
Andreas Olofsson
3ae9c26d38 Changing shift/load order 
- Load should always have higher priority, but load is blocked if there is a pending shift anyway...
 2016-03-21 20:50:41 -04:00