Andreas Olofsson
3a8f81d4a3
Changing single port memory to be ASIC friendly
2015-12-03 18:01:21 -05:00
Andreas Olofsson
7b8460b145
Fixing up issues with database reorg
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- Not sure where the prog_full issue popped up from. (sign of disorganized databsae)
-
2015-11-30 15:07:28 -05:00
Andreas Olofsson
19fa611bb9
Massive reorganization to impove reuse
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- adding more chip code
- pushing memory stuff into common
- making common "oh_" naming class
-
2015-11-30 13:45:49 -05:00
Andreas Olofsson
9ddd71024d
Fixing system_bd interface for "mailbox_irq" signal
2015-11-29 12:41:53 -05:00
Andreas Olofsson
162cb022f9
Adding pushback circuit to stimulus
2015-11-24 01:04:14 -05:00
Andreas Olofsson
074186bd31
Adding new axi utility lib to sim file + README cleanup
2015-11-18 23:33:08 -05:00
Andreas Olofsson
aff0d82a30
Fixing issue with bit stream write
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- Script was exiting before bit stream was written
2015-11-17 22:13:46 -05:00
Andreas Olofsson
3102d6cd44
Adding comments
2015-11-16 09:58:47 -05:00
Andreas Olofsson
4b384be602
Fixing edge align circuit
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- duh error
- making output positive edge aligned, the negedge nastyness should be maintained within module...
2015-11-14 23:33:48 -05:00
Andreas Olofsson
e70c51670c
Adding edge align circuit
2015-11-14 22:41:19 -05:00
Andreas Olofsson
75cef84075
Timescale stuff
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- Need to look into this again, gotchas here
-
2015-11-13 16:25:38 -05:00
Andreas Olofsson
3f1296b099
Cleanup
2015-11-12 10:50:05 -05:00
Andreas Olofsson
a9e034bef9
Bringing access low during wait
2015-11-12 00:58:06 -05:00
Andreas Olofsson
04cd179f5a
Lint fixes for icarus/verilator
2015-11-09 21:57:25 -05:00
Andreas Olofsson
55ba8ff635
Cleaning up warnings from FGPA tools
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- removing unconnected ports
- only one rst input for async_fifo
- synchronizing the reset input toe emaxi fifo
2015-11-09 13:23:40 -05:00
Andreas Olofsson
cf2123ce88
Don't generate fifo during packaging
2015-11-09 13:22:27 -05:00
Andreas Olofsson
64f55eb792
Fix 0 day bug...
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- this shows why it's so important to read the warnings. (circuit was broken!)
2015-11-09 13:21:26 -05:00
Andreas Olofsson
01fd24e069
Fixing synchronization reset speed path
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- This seems silly, why even have a syncrhonizer
- Safe to set speed path?
2015-11-09 00:16:35 -05:00
Andreas Olofsson
875e4213a5
Adding attributes to sync logic
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- Otherwise tool was throwing away logic and timing incorretly.
- This is why you HAVE to isolate this logic! Solve the problem once for all logic and for everyone.
2015-11-08 23:30:47 -05:00
Andreas Olofsson
b6c95e5b94
Cleanup
2015-11-06 22:34:08 -05:00
Andreas Olofsson
979b20a451
Fixing name on fileset for constraints
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- Apparantly has to be fixed to constr&^(I&W)%
2015-11-06 22:32:46 -05:00
Andreas Olofsson
ebf2e861de
Need to validate design before writing tcl
2015-11-06 20:47:35 -05:00
Andreas Olofsson
a683e58597
Associating clock with bus interface
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- This should be moved to the block , block specific...
2015-11-06 20:45:38 -05:00
Andreas Olofsson
63bf5d25a4
Moving to active low reset
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- Because this is the right thing to do for chips
- Not going to tell you why...
2015-11-06 16:51:57 -05:00
Andreas Olofsson
322dc1119c
Adding standard modules for reset and data sync
2015-11-06 16:51:35 -05:00
Andreas Olofsson
8a89b7e185
Adding more structured vivado build files
2015-11-06 14:11:46 -05:00
Andreas Olofsson
3969e6d19e
Moving to MIT license
2015-11-06 11:25:05 -05:00
Andreas Olofsson
751ad95a16
Adding parallella dir
2015-11-06 07:02:04 -05:00
Andreas Olofsson
92272e211d
Adding missind dirs in comamnd file
2015-11-04 20:04:44 -05:00
Andreas Olofsson
63e0017275
Stimulus end of test issue
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- Still not 100% on this...but test passes
- Teset was hanging even though stim_done went high. Ticks not advancing, pointing towards comb loop, but what is different at end of test?
- Now to test read/writes of registers from axi and set the idelay registers
2015-11-03 19:56:27 -05:00
Andreas Olofsson
3f9ac4d745
Adding missing files
2015-11-03 14:16:50 -05:00
Andreas Olofsson
85cc46567a
Removing reset
2015-10-08 10:45:27 -04:00
Andreas Olofsson
2e9744cd44
Changing default to simplify instantiation
2015-05-14 22:46:23 -04:00
Andreas Olofsson
35d86bcdc3
Adding pulse_stretcher circuit
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-simple but powerful for syncing from fast to slow clock domains
2015-05-14 22:45:32 -04:00
Andreas Olofsson
61de7c366a
Cleaning up clock divider
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-moving 90 degree phase shift to PLL
2015-05-06 12:26:07 -04:00
Andreas Olofsson
b05f236d13
Clocks on during reset
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-Otherwise we can't do sync reset anywhere
-glitch on exit from reset? Do we care? Everything is static
-Need to check this again!
2015-05-03 23:21:10 -04:00
Andreas Olofsson
21dcedbda2
Adding simple priority arbiter
...
Yes it's simple, but youl should never have to rewrite this code
For larger arbiters, too much risk of making a mistake...
Arbitration mistakes aver nasty to find and nasty to debug!
2015-05-03 23:19:40 -04:00
Andreas Olofsson
754aae749f
Adding various helper modules
2015-05-01 17:13:21 -04:00
Andreas Olofsson
0f0ff55928
Verilator based lint cleanup
2015-04-23 18:57:55 -04:00
Andreas Olofsson
2b22d1c4af
Adding emesh to packet converters
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-getting tired of all the typing after all....
2015-04-22 16:43:52 -04:00
Andreas Olofsson
c01a9fbd27
Adding basic readme files
2015-04-21 21:49:40 -04:00
Andreas Olofsson
8adc060bc8
Clock divider fixup
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-changed to latest and hopefully final register config
-fixed functional bugs (was broken..)
-added xor for sensing change of clock frequency
2015-04-18 16:12:43 -04:00
Andreas Olofsson
dca611c5ba
Getting all the clk config numbers aligned
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Not changing these again!!
2015-04-16 22:48:31 -04:00
Andreas Olofsson
068d63279b
Changing ESYSCLK definition (again.....)
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old implementation felt too "cutsy"
this makes for a cleaner usage model (simple shift with param)
also splitting out enable but, not making the CTIMER mistake again
2015-04-16 22:31:36 -04:00
Andreas Olofsson
846bfa3357
Fixing startup issues in transmit path:
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-adding reset signals to synchronizer to solve startup issues
-setting config in test bench for speedup, default reg config now correct
-fix (my) stupid bug in etx_arbiter
-adding reset to fifo (todo: review this!)
-reviewing "all red" from waveforms is a must. Red (x) on data is ok, but leaving them on control signals is asking for trouble. Better safe than sorry when it comes to reset.
2015-04-15 16:33:20 -04:00
Andreas Olofsson
710c48b880
Fixed clock divider circuit
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-changed ecfg clock default values, elink default is now the PLL clock/128 coming out of reset
-should work in any implementation?
-still have to implement the Xilinx specific stuff
2015-04-15 14:56:29 -04:00
Andreas Olofsson
69f3df4140
Continued work to create clean design:
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-pll bypass for clocks (customer request)
-adding dividers on all clocks (tx/cclk)
-adding reset block (clearer)
-using commong clock_divider block
-need to clean up divider block later today, slightly broken:-)
2015-04-15 11:54:43 -04:00
Andreas Olofsson
04c65d3570
Adding back the "common" directory
2015-04-14 23:22:29 -04:00
Andreas Olofsson
21a058f696
Cleanup
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Removed useless common directory
Fixed vivados permissions on file
2015-04-11 00:12:57 -04:00
Fred Huettig
1bc118cfcd
Merge branch 'elink_redesign' of https://github.com/Parallella/parallella-hw into elink_redesign
...
Conflicts:
fpga/src/ecfg/hdl/ecfg.v
2014-11-19 12:29:35 -05:00
