Andreas Olofsson
d81bb66d73
Writing while full is aserted
2015-08-14 17:15:38 -04:00
Andreas Olofsson
9bc40a8355
Fixing wait issue
...
-Removing the wait signal from the pipeline
-Assumption is that the prog_full is used on fifo, allowing two entries
to be captured in fifo.
-May revisit this at some time...
2015-08-14 17:13:52 -04:00
Andreas Olofsson
ede8656081
Fixing mutual exclusive bug on receiver
...
-When a read response is detected, there should be no spurious transactions to the RD/WR request fifos.
-Move the "filter" backt to the erx_protocol block
-Removed the remap bypass signal (was hacky)
-Passes simulations again..
2015-08-14 15:37:37 -04:00
Andreas Olofsson
21686d31cc
Reorg for xilinx projects
...
-making more modular
-still need to clean up duplucate files
2015-08-08 12:29:00 -04:00
Andreas Olofsson
b0a321a588
Clarified enable/disable status
...
-For now RX/TX is always on
-At some point make default off?
2015-08-07 09:25:41 -04:00
Andreas Olofsson
8e32299f2c
Copyright cleanup
2015-08-07 09:19:37 -04:00
Andreas Olofsson
617e5f76de
Updating interface description
2015-08-07 09:15:10 -04:00
Andreas Olofsson
f908acc259
Updating docs
...
-clarifications
-removing TX DMA
2015-08-07 09:09:42 -04:00
Andreas Olofsson
7df92eb1f0
Removing DMA from transmit
...
* Seems like a useless feature. Why autogenerate the transactions at the transmit side. This should always be done at the receive side to minimize bits moving across the link. Can't really see a use for it anymore so I am removing it.
* If you want to hack the design to reduce latency, you can always grab the raw etx_core and drive signals directly through write port.
* May consider adding a fourth port to etx to allow bypassing the link interfac?
* Add an ifdef to bypass the fifos?
2015-08-07 09:05:11 -04:00
Andreas Olofsson
5e50d78c51
Merge branch 'master' of https://github.com/parallella/oh
2015-08-07 07:56:44 -04:00
Andreas Olofsson
36e8f78370
README changes and various fixes
2015-08-07 07:56:30 -04:00
Andreas Olofsson
cbc029521b
Update README.md
2015-08-04 18:08:02 -04:00
Andreas Olofsson
0a381ccffe
Merge pull request #7 from olajep/master
...
Fixes
2015-07-07 08:40:00 -04:00
Ola Jeppsson
4f48bdca03
projects/axi_elink: Add missing fifo
...
Add fifo_async_104x32.xci
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
2015-07-05 23:51:46 +02:00
Ola Jeppsson
4df38ca35e
elink: Update scripts
...
Use paths relative top top_srcdir (so scripts can be run from any
directory).
Add missing files
elink_example was renamed to axi_elink?
Fails at placement.
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
2015-07-05 23:51:19 +02:00
Ola Jeppsson
5e16c906f7
Update README
...
Add (work-in-progress) build instructions.
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
2015-07-05 23:32:28 +02:00
Ola Jeppsson
47fe8ff923
Add configure script
...
Generates makefile from template in pwd.
Makes out of tree building simpler.
Configures top_srcdir and top_builddir.
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
2015-07-05 23:30:55 +02:00
Ola Jeppsson
3db4e49675
elink: Convert package_axi_elink to use helper script
...
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
2015-07-05 19:43:32 +02:00
Ola Jeppsson
d03e70a016
Add Makefile
...
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
2015-07-05 19:43:01 +02:00
Ola Jeppsson
11307d072f
Add ip generation helper script
...
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
2015-07-05 19:40:30 +02:00
Andreas Olofsson
c627827a6b
Fifo cleanup
...
-Adding model (one source..)
-generate for 104x32 for xilinx
-making prog_full the default full indicator
-bringing out almost_full for future use
-fixing interface change in all modules
2015-07-02 16:59:38 -04:00
Andreas Olofsson
9fb9dc1cd5
Adding IP packaging script
2015-07-02 16:58:43 -04:00
Andreas Olofsson
9379484f65
Fifo parameter change
...
-Changing parameter name to DW
-Making depth 32 for axi interfaces
(tune this later...)
2015-07-02 16:55:42 -04:00
Andreas Olofsson
f1b37ab4c4
Ephycard should not be default
2015-07-02 16:54:31 -04:00
Andreas Olofsson
d6f61784b0
Update dv paths
...
-includes inside files (methodology change)
-adding ip paths
2015-07-02 16:48:14 -04:00
Andreas Olofsson
e28cd3cb97
Adding search path for include file
2015-07-02 16:47:07 -04:00
Andreas Olofsson
368836ab9b
Adding back a better fufu test vector
2015-07-02 16:46:33 -04:00
Andreas Olofsson
0c66100d6d
Adding half full signal to fifo
2015-07-02 15:00:18 -04:00
Andreas Olofsson
51a642a7b7
Adding 32 deep interface fifo for AXI
...
-needed to support burst properly
2015-07-02 14:59:57 -04:00
Andreas Olofsson
c0f5c23cb0
Merge pull request #6 from plindstroem/patrik
...
Patrik
2015-07-02 09:26:22 -04:00
Patrik Lindström
a20c9f25ec
clean up
2015-07-02 15:01:33 +02:00
Patrik Lindström
b9558a70c8
change path
2015-07-02 14:53:21 +02:00
Patrik Lindström
4a749bf2d8
timing fixes
2015-07-01 00:14:46 +02:00
Patrik Lindström
6d13611f21
script fixes
2015-06-30 16:02:39 +02:00
Patrik Lindström
7b1e712884
script fixes
2015-06-30 15:00:32 +02:00
Patrik Lindström
667c7cb6a8
script fixes
2015-06-30 14:56:27 +02:00
Patrik Lindström
d0d6cc0d4a
Fixed file locations
2015-06-30 14:12:04 +02:00
Patrik Lindström
a284dff462
Bug fixes
2015-06-30 14:04:16 +02:00
Patrik Lindström
6a232d7834
adding project folder
2015-06-30 13:58:20 +02:00
Patrik Lindström
634ff371ac
Bug fixes
2015-06-30 13:32:05 +02:00
Patrik Lindström
48fdf2d782
Added iostandard parameter
2015-06-30 12:44:22 +02:00
Patrik Lindström
f232d9d297
Changed rx_ref_clk PLL divider
2015-06-30 12:35:38 +02:00
Patrik Lindström
8c0dbffb61
Added different IDW for m_axi and s_axi
2015-06-30 12:31:14 +02:00
Andreas Olofsson
537bb6a330
Cleanup
2015-06-25 22:14:19 -04:00
Andreas Olofsson
e960b6f7c0
Adding IP package reference script
2015-06-25 22:14:05 -04:00
Andreas Olofsson
fc31ad57fd
Reorg
2015-06-25 19:52:28 -04:00
Andreas Olofsson
d9155f6538
Placeholder for elink
2015-06-25 16:17:20 -04:00
Andreas Olofsson
eb7028fdbf
Reorg
2015-06-25 16:13:20 -04:00
Andreas Olofsson
badac2aa76
Name changes for signal grouping
2015-06-25 16:09:05 -04:00
Andreas Olofsson
b0c7b75407
Adding OBUF model
2015-06-25 15:42:20 -04:00
