Andreas Olofsson
d83efbdb8e
Cleaning up initial constraints
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-Now generates bit stream
-It won't work, but it's a start...
2015-05-08 20:56:33 -04:00
Andreas Olofsson
a52fa86edb
Fixing instances errors from fpga synthesis
2015-05-08 20:55:31 -04:00
Andreas Olofsson
9793be3bf0
Fixing crucial error in documentation
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-Nothing worse than incorrect comments!
2015-05-07 23:52:02 -04:00
Andreas Olofsson
38d7fe1af9
Clock cleanup
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-Moving to single clock
-Unifying the timescale (1ns period)
-Stopping access when done with stimulus file
2015-05-07 23:46:32 -04:00
Andreas Olofsson
1f6c18a764
Using fifo_cdc instead of fifo_async
2015-05-07 23:45:36 -04:00
Andreas Olofsson
c51f8f3dc9
Adding clock buffer
2015-05-07 23:44:39 -04:00
Andreas Olofsson
773bab5c6a
First version of synthesis tcl scripts for elink example
2015-05-07 23:43:05 -04:00
Andreas Olofsson
ba32323306
Cleaning up clocks
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-moving to "real" Xilinx PLL instantiation
-one PLL for CCLK one for LCLK
-removing clock dividers, can't work at speed, put inside model
-configuration needs to be done differently
-removing pll_bypass signal, can't work with logic
-clocks should be done with hard macro primitives (no logic)
2015-05-06 12:23:15 -04:00
Andreas Olofsson
4f487d498e
Making simulation more "real"
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-Working with timescale (for viewer mostly)
-Now using TARGET_XILINX as default in sim
2015-05-06 12:21:39 -04:00
Andreas Olofsson
d8b5fa78ef
Adding emesh as basic building block
2015-05-05 21:38:41 -04:00
Andreas Olofsson
d0439f871f
Adding example design for FPGA
2015-05-05 21:37:17 -04:00
Andreas Olofsson
c843fc5fe0
Renaming for my sanity (etx/erx split)
2015-05-05 14:56:35 -04:00
Andreas Olofsson
300e5a14fc
Reorg
2015-05-05 14:47:21 -04:00
Andreas Olofsson
a3cfa17b06
Removing old module
2015-05-04 22:38:28 -04:00
Andreas Olofsson
de74f8accc
Removed synchronizer, not needed
2015-05-04 22:34:14 -04:00
Andreas Olofsson
b2846c5312
MILESTONE: Read/write works back and forth
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-Pipeline looks good, now need to test clk1>>clk2 and clk2>clk1
-Still not completely happy with reset (using async for now)
2015-05-04 17:13:51 -04:00
Andreas Olofsson
570fbffd7f
Baking in the IO wait signal into rd/wr wait
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-Separate waits for rd/wr wait
-Adding wait to protocol block as well
-io_wait always goes through
-using active frame signal to select/clear data for output
2015-05-04 17:10:32 -04:00
Andreas Olofsson
dcf72537e4
Separate rd/wr stalls
2015-05-04 17:09:50 -04:00
Andreas Olofsson
0aba754b7e
Cleanup
2015-05-04 10:54:42 -04:00
Andreas Olofsson
72aff72558
MILESTONE: register read/write working!
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-Bullet proof clock domain crossings!
2015-05-04 10:49:17 -04:00
Andreas Olofsson
bb8f5f861b
Moving the read response to separate group (not register)
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Why?
1.) This will allow for support of multiple outstanding channels at some point
2.) Much easier to debug, can tag transactions in test bench
2015-05-04 10:41:42 -04:00
Andreas Olofsson
e9d6794833
Blocking TX outgoing transcations on LINKID match
2015-05-04 10:41:14 -04:00
Andreas Olofsson
25b0b188ff
Implementing register readback on read response channel
2015-05-04 10:40:43 -04:00
Andreas Olofsson
6907d39490
Making readback work
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-Simplifying logic for rx_en
-Reaback data was incorrectly pipelined (one too many)
2015-05-04 10:39:01 -04:00
Andreas Olofsson
b63de8b1d8
Filter the txwr access
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We don't want reset/clock transaction to propagate through etx!
2015-05-04 10:37:27 -04:00
Andreas Olofsson
1ee720fc67
Organization changes
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-dma with packet format
-using the fifo_cdc block
2015-05-03 23:29:32 -04:00
Andreas Olofsson
51b14f41ce
wait in vs. wait out confusion
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wait_out is the signal being driven out telling someone else to wait
wait_in is the incoming signal telling "you" to wait".
2015-05-03 23:26:43 -04:00
Andreas Olofsson
cfe811e7a7
Complete redesign
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-Following access,wait, packet pipeline format
-Use a priority arbiter
2015-05-03 23:25:19 -04:00
Andreas Olofsson
47a143eada
Turning on clocks by default (low frequency)
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Seems safer
2015-05-03 23:23:28 -04:00
Andreas Olofsson
781121fc61
Cleanup
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-setting DMA access to zero for now
-taking away wait for elink2 (messes up the access pattern)
-fixing typo in register mape ERX
2015-05-02 23:04:13 -04:00
Andreas Olofsson
2da588721a
Fixed verilog syntax issue
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-Not sure what parameter couldn't be used directly here?
-Works fine when parameter is assigned to wire.
2015-05-02 23:03:14 -04:00
Andreas Olofsson
dcd2d0b111
Clock/reset fixes
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-Making reset async
-lclk_div4 always on (makes reset safer, not a big loss)
-filtering non-matching transactions
2015-05-02 22:42:33 -04:00
Andreas Olofsson
cb9a1f50dd
Fixing ecfg_clocks
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-Was missing clock connection
-Adding ID to match only to the right transcations
2015-05-02 22:40:27 -04:00
Andreas Olofsson
ebd9a89afd
Adding constants to handle model
2015-05-02 21:30:26 -04:00
Andreas Olofsson
56fa70c0dd
Connecting wait output from e16_model
2015-05-02 21:29:43 -04:00
Andreas Olofsson
130caa64b6
E16 model cleanup
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-fixing false error message
-removed emesh_interface isntance (not needed..)
-set floating inputs to zero
2015-05-02 21:28:09 -04:00
Andreas Olofsson
e5fc895a25
Cleanup
2015-05-01 18:33:29 -04:00
Andreas Olofsson
340d99cab1
Instance renaming
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Will help with FPGA synthesis reports (uniqueness needed sometimes)
2015-05-01 18:19:36 -04:00
Andreas Olofsson
8461277ab1
Complete redesign of configuration register file
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-There is now only one clock domain crossing involved with the reg files/ All clock domain crossings use the same 104 bit wide async fifo! If it's broken we are screwed, if it works we are perfect!
-Configuration can be done from host through txwr/txrd path of any register
-The RX IO pins can only access the RX side of the design
2015-05-01 17:58:16 -04:00
Andreas Olofsson
f215e07ce9
Updated to fit new ERX_RR register
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-Read response now returns to a memory mapped register
2015-05-01 17:53:55 -04:00
Andreas Olofsson
23cb2acb31
Updated constants file to fit new register map
2015-05-01 17:52:55 -04:00
Andreas Olofsson
4059a6eaa2
Created unified one clock modular confi for RX/TX
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-Solves clock domain crossing uglyness
-Very nice and clean!!
-Only compromise is that the RESET and CLOCK registers aren't readable
2015-05-01 17:51:12 -04:00
Andreas Olofsson
20534a6ed1
Added testmode to transmitter
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-pin driven testmode driven..b/c fpga designers often don't like software
-and because it's really convenient, press a push button and see a pattern appear
-removed protocol description, goes in README.md, there should only be one source for documentation
-shortened signal names for ecfg
-changed to "clk" input now that everything is single clock
2015-05-01 17:47:24 -04:00
Andreas Olofsson
93f0fb6220
README cleanup
2015-05-01 17:42:12 -04:00
Andreas Olofsson
08b871941d
Adding e16 elink golden reference to dv environment
2015-05-01 17:32:52 -04:00
Andreas Olofsson
0ca303432b
Cleanup
2015-05-01 17:31:45 -04:00
Andreas Olofsson
800dacdff4
Updated register map and interface
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-Changed DMA descriptor locations
-Changed colid/rowid -->chipd[11:0] (more consistant)
-Added access column (R/W)
2015-05-01 17:27:24 -04:00
Andreas Olofsson
e168bd5f98
reorg
2015-05-01 17:21:45 -04:00
Andreas Olofsson
0762b90fef
Reorg
2015-05-01 17:21:21 -04:00
Andreas Olofsson
d541a261a6
Adding Epiphany16 elink RTL implementation as reference
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This is pretty big, wonder if anybody will notice?
Why am I doing this?
Because the elink has been haunting us for years. This way we will finally have a "golden reference" simulator model for those who insist on designing their own elink protocol (aginst my recommendation). This is equivalent to having a "bfm-bus functional model" for AXI. The spec is nice, but it's always up for interpretation. We have had some issues with documenting the protocol corretly. While we will fix the documentation, please note that the source code and design verification environment will always be the golden version. This is after all "the silicon".
For me and everyone else, it becomes part of the open source design verification environment to test the elink.
Enjoy....
2015-05-01 17:14:50 -04:00
