Andreas Olofsson
7ab3b3a8f8
Fixed floating net bug
2015-04-23 20:05:00 -04:00
Andreas Olofsson
74fe62e94d
Broken testbench connections
2015-04-23 20:04:03 -04:00
Andreas Olofsson
0f0ff55928
Verilator based lint cleanup
2015-04-23 18:57:55 -04:00
Andreas Olofsson
155f6a9401
File cleanup
2015-04-23 18:10:07 -04:00
Andreas Olofsson
ec68dddd99
Packet interface changes
2015-04-23 18:09:16 -04:00
Andreas Olofsson
842dd60b3e
Adding DMA register to regmap
2015-04-23 18:08:52 -04:00
Andreas Olofsson
c76bce1ea3
Changing so basic elink unti is without AXI
2015-04-23 18:08:20 -04:00
Andreas Olofsson
fcf5bf010f
Splitting register file into separate pieces
2015-04-23 18:07:50 -04:00
Andreas Olofsson
ec0c9ce835
Changing to packet interface
2015-04-23 18:07:27 -04:00
Andreas Olofsson
ed0b8c2539
Major RX change:
...
-renamed interfaces to rxwr,rxrd,rxrr (much simpler to remember for me)
-packet interface change
-removed wait signals from dataout field
-added dma, emmu, mailbox, config register
-instantiating fifo_sync raw (without wrapper)
2015-04-23 18:04:39 -04:00
Andreas Olofsson
2707541eab
Adding DMA source and changing interface
...
-DMA added as a master driving out transactions
(this is going to be great!!)
-Changing to packet interface
2015-04-23 18:03:10 -04:00
Andreas Olofsson
842a6d894a
Fixing enable/reset:
...
-Removing enable from ISERDES, not healthy
-Moving all logic to protocol block. (this is an IO block)
-Removing tow redundant pipeline stages (check this??)
2015-04-23 18:01:19 -04:00
Andreas Olofsson
7418d45f5e
Cleanup
...
-Packet interface change
-Adding RX enable logic with synchronizer (better place than erx_io)
2015-04-23 17:59:36 -04:00
Andreas Olofsson
d9525b6ae4
Major upgrade
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-Adding DMA, EMMU, CFG
-Removing redundant signals
-Changing to packet interface
2015-04-23 17:58:18 -04:00
Andreas Olofsson
9a614d1094
Packet interface change
2015-04-23 17:57:24 -04:00
Andreas Olofsson
44f162ec09
Packet interface change
...
-Changed packet interface
-Removed rd/wr from block, was pass through
2015-04-23 17:56:15 -04:00
Andreas Olofsson
1e1644138e
Splitting register file (rx,tx,base)
...
The goal is to have 100% independence in RX and TX pipes
2015-04-23 17:50:45 -04:00
Andreas Olofsson
0d10fbd26f
Adding more docs
2015-04-23 17:50:16 -04:00
Andreas Olofsson
cc5f165454
Clarified lclk names
2015-04-22 15:03:24 -04:00
Andreas Olofsson
c225349639
Updated clocking diagram
2015-04-22 15:02:50 -04:00
Andreas Olofsson
703da8445b
deleted junk
2015-04-22 15:02:31 -04:00
Andreas Olofsson
bc71401888
Adding elink clocking diagram
2015-04-22 13:58:51 -04:00
Andreas Olofsson
797d836a02
Renaming constants file
2015-04-22 13:56:48 -04:00
Andreas Olofsson
617214cc90
Cleanup
2015-04-22 13:56:29 -04:00
Andreas Olofsson
ba8f400a37
oops
2015-04-21 21:50:03 -04:00
Andreas Olofsson
c01a9fbd27
Adding basic readme files
2015-04-21 21:49:40 -04:00
Andreas Olofsson
275264c84d
Reorg
2015-04-21 21:33:49 -04:00
Andreas Olofsson
035b3c9ba5
Milestone: WRITE AND READ FROM HOST WORKS!
2015-04-21 17:16:20 -04:00
Andreas Olofsson
b89d6222d8
Adding test for readback from host
2015-04-21 17:15:56 -04:00
Andreas Olofsson
d0b04687ea
Bug fix, missing pipeline stage on read response
...
-Apparantly old FIFO was not pipelined (IE data comes back same cycle).
-Not knowing the Xilinx logic, I made it a regular one cycle pipeline
memory based FIFO
2015-04-21 17:14:30 -04:00
Andreas Olofsson
fc3926ceb1
Added wait signal for reads
2015-04-21 17:13:53 -04:00
Andreas Olofsson
0d42736914
Implemented enesh memory
...
-not parametrized
-keeping 64 bit wide for now
2015-04-21 17:13:09 -04:00
Andreas Olofsson
2369e92ffa
Bug fix, missing "data hold" stage
...
Hadn't realized that the data needed to be held
Need to look at this logic again!
For now going back to old logic
2015-04-21 17:10:51 -04:00
Andreas Olofsson
e033e233d0
Integrating emesh memory module
...
-This will flush out the final read response path
2015-04-20 23:07:13 -04:00
Andreas Olofsson
4c44c59079
Message box working...
...
-More testing needed!
2015-04-19 21:55:07 -04:00
Andreas Olofsson
6cc5d6de90
MMU working...
...
-Needs more testing
2015-04-19 21:36:47 -04:00
Andreas Olofsson
7c93c565e9
Adding back awid, arid, lock to AXI interface
2015-04-18 17:35:22 -04:00
Andreas Olofsson
44a4d0e669
Adding gtkwave signals file
2015-04-18 16:42:34 -04:00
Andreas Olofsson
9e931c47ec
Cleanup
2015-04-18 16:26:32 -04:00
Andreas Olofsson
f141a0e320
Clock cleanup
...
-Adding enable signal to clock out. Definitely right decision to keep
separate bit from the divider field.
-Fixed settings for to fit new register field
-XILINX version is still broken!!
2015-04-18 16:24:26 -04:00
Andreas Olofsson
b30dbe6005
Fixed to fit with new register map
2015-04-18 16:23:35 -04:00
Andreas Olofsson
00a921b839
Changed register map
...
-Moved "groups" to E,D,C
-Changed names to EL* (shorter is better, clear enough)
-Moved order to fit logical operation during init
-Moved embox registers to MMR group
DONE!
2015-04-18 16:21:45 -04:00
Andreas Olofsson
27087fb736
ESAXI cleanup
...
-widen address bus to 32 bits
-blocking access to elink on ecfg access
-fixing decoding for embox
2015-04-18 16:18:41 -04:00
Andreas Olofsson
baf6cc5a62
Removed synchronizer on TXLCLK
2015-04-18 16:17:44 -04:00
Andreas Olofsson
643ceed432
Adding manual test feature to testbench
...
-This is as far as I go with fufu testing (random next)
-Add basic test for cleaning up reads/writes
-104 bit packet format for driving transactions, very useful
2015-04-18 16:14:53 -04:00
Andreas Olofsson
80bb50703b
Adding basic elink read/write test
2015-04-18 16:12:04 -04:00
Andreas Olofsson
9c24869d72
Simplifying register names
2015-04-18 09:49:54 -04:00
Andreas Olofsson
3c2b760a2f
Prettifying format..starting to look decent
2015-04-18 07:51:13 -04:00
Andreas Olofsson
47bf283f05
Adding experimental README file
2015-04-18 07:39:38 -04:00
Andreas Olofsson
85db5d9de0
Spell checking comments
...
First time ever using spell cheker in EMACS. Hard to believe...but it's true!
I am sure this speaks volume for how little I have commented my code over the years!
2015-04-18 06:36:33 -04:00
