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Author SHA1 Message Date
Andreas Olofsson
d9ea47a88d Common library cleanup 2016-03-22 09:19:39 -04:00
Andreas Olofsson
6f60b19c8f Adding links to all common modules 2016-03-22 09:17:01 -04:00
Andreas Olofsson
401bc8319a README formatting 2016-03-22 08:32:09 -04:00
Andreas Olofsson
c3b83621e0 Reorg cleanup 2016-03-22 08:27:59 -04:00
Andreas Olofsson
7094173ae9 Reorg! Why? 
- The top level directory was not scaling, too imposing
- Friendlier to download a repo and see a finite number of top level dirs
- We are just getting started...
 2016-03-22 08:13:40 -04:00
Andreas Olofsson
a6f1dc8971 Merge branch 'master' of github.com:parallella/oh 2016-03-22 08:01:04 -04:00
Andreas Olofsson
85ecd25268 Remving the ugly wait hack in the stimulus, not the way to drive the pipeline 2016-03-21 20:51:35 -04:00
Andreas Olofsson
3ae9c26d38 Changing shift/load order 
- Load should always have higher priority, but load is blocked if there is a pending shift anyway...
 2016-03-21 20:50:41 -04:00
Andreas Olofsson
a991a4fc06 Fixed mux bug in spi 
- copy paste error
 2016-03-21 20:49:39 -04:00
Andreas Olofsson
bc6641bcd0 Simplifying state machine on spi master 
- Divide and conquer, use the  par2ser wait signal to hold off on read
- Removed the stupid byte done state! Was too complicated.
 2016-03-21 20:48:18 -04:00
Andreas Olofsson
2a993815c3 Fixed readback bug 
- Only readback on reads
 2016-03-21 20:47:48 -04:00
Andreas Olofsson
71230c8c95 Resetting slave par2ser with ss (not nreset!) 
- Shifting out on positive edge of sclk
 2016-03-21 20:46:05 -04:00
Andreas Olofsson
7b3ca453f4 Looping back master spi access/packet to driver/stimulus 2016-03-21 20:27:10 -04:00
Andreas Olofsson
c9b2b9e0d8 Fixing basic spi test to fit new clock divider 2016-03-21 20:26:29 -04:00
Andreas Olofsson
b89f451c2f Fixing basic par2ser stall bug 
- don't start new transfer until current transfer is done
 2016-03-21 14:32:15 -04:00
Andreas Olofsson
1972fd21b6 Stressing pushback by removing the training wheels 
-Checks block with full throttle and with waits (for debug)
 2016-03-21 14:30:38 -04:00
Andreas Olofsson
d26d3efbc1 Fixing fifo status for mtx 
(signals were unconnected)
 2016-03-21 14:29:59 -04:00
Andreas Olofsson
29ae5b462b Adding mio test to stress fifo 
-pushback looks good!
 2016-03-21 14:29:03 -04:00
Andreas Olofsson
3175010236 MIO debug 
- fixing msbfirst packet mode bug
- fixing lsbfirst packet mode bug
- fixing clkphase writing bug
- changing default to msb first
- making a single DEF_CFG and DEF_CLK parameters (it was getting out of hand)
- improved test to do emode/amode testing, and writing to registers
-"amode" now works!!**
 2016-03-21 13:50:23 -04:00
Andreas Olofsson
87b502ba73 Changing transmit order for mtx_io 
-Making msbfirst the defaualt (looks cleaner on scope)
-Swapping bytes on msbfirst and ddr mode
-Implementing sdr mode on RX
 2016-03-21 13:48:57 -04:00
Andreas Olofsson
8709e0ff08 Adding decoding in MIO dut for register acess 
-no remote addresses should have bits 31:20 set to zero, so this seems like a safe hack for differentiating between data and control instructions
 2016-03-21 13:47:27 -04:00
Andreas Olofsson
18084bf63f MIO cleanup 
-adding target parameter to fifo
-fixing rx protocol bugs
-adding defaults to register file, usually these should be set to zero and
-don't clock gate the DDR TX, just causes output to toggle like clock, BAD!
-fixed status register sticky bug
-adding autoincrement feature in amode
-fixing dut file for new "mio" subsystem
-**emesh packet now goes through in loopback!!!**
 2016-03-21 11:27:35 -04:00
Andreas Olofsson
29aff43b59 Adding mio sub system module 
-Much easier to use and test, includes clockdiv and regs in one module
-Note that it's still possible to use the mio_dp raw if you tie off signals to constants and bring your own clock.
-Having both approachs should make everyone happy. Have found that SW developers usually can't write verilog and HW folks don't know C (so can't write to registers)...
 2016-03-21 11:25:33 -04:00
Andreas Olofsson
dc51ad3935 Adding mio-->emesh interface 
-Select between autoincrement mode and pass through mode with "amode"
 2016-03-21 11:25:03 -04:00
Andreas Olofsson
8633b09de2 Adding constant for mio 
-Not sure the order works here...
 2016-03-21 11:24:19 -04:00
Andreas Olofsson
a2aa5e8b5b Changing CONFIG bitfield in MIO 2016-03-21 11:23:25 -04:00
Andreas Olofsson
35f74f615f Adding build_all script 
-So many modules depend on each other, so you need to ability to compile all when you make a change to a core module
 2016-03-21 11:22:24 -04:00
Andreas Olofsson
7f0491d206 Cleaning up GPIO 
- AW parameter was missing in p2e
- Blocking input data with input enable (alsom done at io pad)
 2016-03-21 11:20:59 -04:00
Andreas Olofsson
93154c38f8 Adding special div2 logic for clock divider 
- Using negedge of clock for phase shifting 2nd clock by 90 degrees. Used by elink and mio
 2016-03-21 11:19:25 -04:00
Andreas Olofsson
3fa5fce86f Cleaning up fifos 
- Making default parameter generic (will need to fix elink next..)
- Brining out fifo status for cdc module, goes to status registers (very useful for debugging)
 2016-03-21 11:18:07 -04:00
Andreas Olofsson
b61d55533e Fixing par2ser bugs 
-access out signal was broken (may need to fix again for spi)
-lsbfirst mode was broken
-made datasize 8 bits at interface
 2016-03-21 11:16:42 -04:00
Andreas Olofsson
490a3f6be1 SPI compilation cleanup 
- due to changes in par2ser and clock divider
- disadvantage of using common modules that change...
 2016-03-21 11:15:41 -04:00
Andreas Olofsson
fec6a98d90 Refactoring mio 
- changing datapath name to mio_dp (new methodology)
- top level should be complete block (with control + clock) for ease uf use
- clock renaming
 2016-03-21 06:15:50 -04:00
Andreas Olofsson
5b799de0eb Augmenting dv for mio 
- now includes mio regs as well
- next: create a complete block, ie dog fooding to include the mio_regs an axi interface, and a decoder interface to make it look like a subsystem (like the elink)
 2016-03-20 22:40:36 -04:00
Andreas Olofsson
5edf209983 New MIO integration 
- removing tx protocol block (reduces to par2ser)
- adding status bits to interface
- adding control signals from mio_regs
 2016-03-20 22:39:22 -04:00
Andreas Olofsson
5ff50f78c0 Fixing mtx io logic 
- adding support for single data rate
- removing wait logic from io registers, should only go to fifo
 2016-03-20 22:37:50 -04:00
Andreas Olofsson
d800325f50 Reformatting to use "N" as the main parameters 
-simpler..
 2016-03-20 22:37:30 -04:00
Andreas Olofsson
308b46366a Refactoring rx to use ser2par block 2016-03-20 22:36:33 -04:00
Andreas Olofsson
c18177c8a7 Adding register 
- These can be used to make the configuration of the mio datapath programmable
- This is what I should have done for the elink. Always separate the control from the datapath!!
 2016-03-20 22:35:43 -04:00
Andreas Olofsson
f6f1009b52 Removing protocol block, redundant 2016-03-20 22:35:30 -04:00
Andreas Olofsson
d1fd144374 New and improved MIO interface 2016-03-20 22:33:57 -04:00
Andreas Olofsson
e5a8227509 Adding features to clock divider 
-splitting out period from phase
-adding a second phase shifted clock (running off one counter)
-adding orthogonal control of rising and falling edge
 2016-03-20 18:17:26 -04:00
Andreas Olofsson
015b969ac2 Making default parameter N=1 for muxes 
- Less reconfiguring of parameters at instantiation time
 2016-03-17 23:41:56 -04:00
Andreas Olofsson
e36a817846 Fixing link script 2016-03-13 09:31:45 -04:00
Andreas Olofsson
4b1372eb3b Implementing GPIO readback circuit 
-added test, looks good
-reduced decoder width to 16 regs (seems reasonable for gpio)
 2016-03-13 09:28:17 -04:00
Andreas Olofsson
4517280e45 Adding emesh readback circuit 2016-03-13 09:27:39 -04:00
Andreas Olofsson
a8182de5e1 Adding environment setup script 2016-03-12 16:49:56 -05:00
Andreas Olofsson
4d172960c1 Renaming the generic dut template file 2016-03-11 16:40:30 -05:00
Andreas Olofsson
e1f8b1d6c4 Adding dummy dut to make autocomplete work in emacs 2016-03-11 16:38:17 -05:00
Andreas Olofsson
74d1a9dc72 Fixing SPI header file inclusion issue 2016-03-11 15:08:01 -05:00