FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-17 20:02:53 +08:00
Code Issues Projects Releases Wiki Activity
296 Commits 7 Branches 1 Tag
Commit Graph

4 Commits

Author SHA1 Message Date
Andreas Olofsson
ec3dbc910a Using async reste on fifo output access signal 
-For cases where there is no clock at output
 2015-05-04 17:07:55 -04:00
Andreas Olofsson
75f653ffd6 Naming cleanup 2015-05-04 10:37:08 -04:00
Andreas Olofsson
19e22c38d7 Adding proper wait to fifo_cdc 
If there is a waitm, we should
1.) Not increment the read pointer
2.) Hold the packet steady until wait signal goes away
3.) Hold access high, keep request intact
 2015-05-03 23:17:23 -04:00
Andreas Olofsson
a58c2d5279 Adding clock domain crossing module for emesh 
-Generic, built for reuse
 2015-05-01 17:13:44 -04:00